Wafer Architect

Austin, Texas, United StatesPosted 2 months ago

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Opens Volantis Semiconductor, Inc.'s own application

Salary: Not stated
Where: Austin, Texas, United States (work mode not stated)
Contract: Not stated
Experience asked: Not stated
Degree asked: Not stated
Languages required: Not stated
Work permit: Not stated
Posted: 2 months ago; 31 Jul 2026

Asks for

The ad says“Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc”
The ad says“Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems”
The ad says“Understanding of memory sub-systems and interactions in multi-die systems”

Values

The ad says“Experience with MCM and chiplet based architectures and architectural partitioning across them”
The ad says“Experience with MCM and chiplet based architectures and architectural partitioning across them”
The ad says“Experience with multi-die designs”
The ad says“Experience in partitioning workloads across multiple chips and chip packages”

What We’re Looking For:

We’re looking for an architect to own the logical architecture for the A-0 and A-1 wafer products. You will work with the XPU/Compute chip architect and the memory architect to synthesize the final wafer-level architecture.

Ideal Background:

An ideal candidate will have:

Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc
Understanding of memory sub-systems and interactions in multi-die systems
Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems

Strongly Preferred:

Experience with multi-die designs
Experience with MCM and chiplet based architectures and architectural partitioning across them
Experience in partitioning workloads across multiple chips and chip packages

Volantis Semiconductor, Inc.

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Asks for

The ad says“Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc”

The ad says“Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems”

The ad says“Understanding of memory sub-systems and interactions in multi-die systems”

Values

The ad says“Experience with MCM and chiplet based architectures and architectural partitioning across them”

The ad says“Experience with multi-die designs”

The ad says“Experience in partitioning workloads across multiple chips and chip packages”