Asks for

The ad says“Expert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques.”
The ad says“We are looking for a Tech Lead, Formal Verification Engineer with 5–10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs' next-generation connectivity and AI infrastructure products.”
The ad says“We are looking for a Tech Lead, Formal Verification Engineer with 5–10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs' next-generation connectivity and AI infrastructure products.”
The ad says“Hands-on experience with one or more formal verification tools – JG, VCF preferably.”
The ad says“Strong scripting skills in Python, Perl, Tcl, or Shell.”
The ad says“We are looking for a Tech Lead, Formal Verification Engineer with 5–10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs' next-generation connectivity and AI infrastructure products.”
The ad says“Strong scripting skills in Python, Perl, Tcl, or Shell.”
The ad says“Strong scripting skills in Python, Perl, Tcl, or Shell.”
The ad says“Expert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques.”
The ad says“Expert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques.”
The ad says“Strong scripting skills in Python, Perl, Tcl, or Shell.”
The ad says“Expert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques.”

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

We are looking for a Tech Lead, Formal Verification Engineer with 5–10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs' next-generation connectivity and AI infrastructure products.

Key Responsibilities

Develop comprehensive formal verification plans from architecture and design specifications by identifying critical design properties, protocol requirements, and micro-architectural invariants.
Develop and execute formal verification environments, assertions, properties, and checkers.
Drive proof convergence through advanced abstraction and complexity reduction techniques.
Collaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.
Evaluate, deploy, and scale formal verification methodologies, flows, and tools across projects.
Improve verification productivity through reusable methodologies, automation, and best practices.
Ensure comprehensive design correctness and provide technical leadership and mentorship across multiple projects.
Drive bug triage, root-cause analysis, and resolution in collaboration with cross-functional teams.
Support project planning by estimating verification effort, tracking execution progress, identifying risks, and driving mitigation plans.
Participate in design reviews and contribute to verification sign-off strategies and quality metrics.
Promote assertion-driven design practices and formal verification adoption across engineering teams.

Required Qualifications

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
5-10 experience in semiconductor verification, including significant formal verification experience.
Expert knowledge of SystemVerilog, SVA,Verification planning & closure and ABV verification techniques.
Hands-on experience with one or more formal verification tools – JG, VCF preferably.
Experience verifying complex protocols, control logic, and SoC or subsystem-level designs.
Strong scripting skills in Python, Perl, Tcl, or Shell.
Excellent analytical, debugging, and problem-solving capabilities
Experience leading technical efforts or mentoring team members.
Strong communication and cross-functional collaboration skills.

Preferred Qualifications

Experience with industry-standard formal verification tools such as JasperGold, VC Formal, or equivalent solutions.
Experience verifying high-speed protocols and interfaces including PCIe®, UALink™, CXL®, Ethernet, SerDes, or related technologies.
Knowledge of NoC architectures, cache coherency protocols, memory subsystems, and interconnect fabrics.
Experience with formal bug hunting, proof-based verification, and coverage-driven verification methodologies.
Prior experience leading technical teams and mentoring engineers.
Exposure to simulation, emulation, and the broader verification lifecycle is a plus.
Track record of contributing to successful silicon tape-outs.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Asks for

Values