Asks for

The ad says“Knowledge of IC chip development flow, design rule methodology, basic analog/digital circuits concepts, and statistical theory.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Familiar with layout design tools, wafer-level probing system and characterization methodology, data analysis tools and FA techniques. Experience of advanced eNVM evaluation/characterization is a plus.”
The ad says“Familiar with layout design tools, wafer-level probing system and characterization methodology, data analysis tools and FA techniques. Experience of advanced eNVM evaluation/characterization is a plus.”
The ad says“Knowledge of IC chip development flow, design rule methodology, basic analog/digital circuits concepts, and statistical theory.”
The ad says“Familiar with layout design tools, wafer-level probing system and characterization methodology, data analysis tools and FA techniques. Experience of advanced eNVM evaluation/characterization is a plus.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Knowledge of IC chip development flow, design rule methodology, basic analog/digital circuits concepts, and statistical theory.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Familiar with layout design tools, wafer-level probing system and characterization methodology, data analysis tools and FA techniques. Experience of advanced eNVM evaluation/characterization is a plus.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Knowledge of IC chip development flow, design rule methodology, basic analog/digital circuits concepts, and statistical theory.”
The ad says“Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.”
The ad says“Familiar with layout design tools, wafer-level probing system and characterization methodology, data analysis tools and FA techniques. Experience of advanced eNVM evaluation/characterization is a plus.”

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Meet the Team

The Foundry Engineering team puts the silicon into Silicon Labs. We interface between silicon wafer foundries and our design and CAD groups to make sure we are using the right process technologies. We ensure that the options, technology files, and models are enhanced to ensure first time silicon success. Our work falls into three areas: 1) bringing in new silicon process technologies, 2) guiding IC products through the design and qualification phases, and 3) maintaining high die yield and solving manufacturing problems.

We are looking for an engineer who is accountable and has initiative to solve challenging problems. You need to be able to dissect the problem, propose solutions, build a consensus on how to proceed, consider the constraints, and drive the execution, analysis, and implementation. If you are thorough, dedicated to quality, analytical, and enjoy collaborating with diverse team members, we want to hear from you.

In this role you will reinforce the team to support new process bring-up & NPI (New Product Introduction) development

Responsibilities

Support new process bring-up through technology assessment, testchip design & characterization.
Support NPI development on resolving design obstacles, executing tapeout & wafer plans, prototype qual, and production launch & ramping.
Interface between operation teams and foundry suppliers for better communication and tackle logistical & technical issues.

Skills You Will Need
Minimum Qualifications:

Master’s/PhD degree in EE, Physics, Material Science or related. Minimal 3 years’ experience.
Solid understanding of semiconductor device physics (PN junction, MOSFET, etc) and intrinsic reliability (HCI, BTI etc), GDS tape-out and mask-making flows, and wafer fab process integration. Experience in advanced-node fab is a plus.
Familiar with layout design tools, wafer-level probing system and characterization methodology, data analysis tools and FA techniques. Experience of advanced eNVM evaluation/characterization is a plus.
Knowledge of IC chip development flow, design rule methodology, basic analog/digital circuits concepts, and statistical theory.
Good communication skills and ability to work multi-tasks mode, including support multiple time-zone teams.

Benefits & Perks:
You can look forward to the following benefits:

Insurance plans with Outpatient cover
Flexible work policy

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Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Asks for

Values