Asks for

The ad says“Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.”
The ad says“Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.”
The ad says“Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.”
The ad says“Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.”
The ad says“Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.”
The ad says“Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level.”
The ad says“Solid understanding of low-power design techniques and power-aware physical implementation.”
The ad says“Proficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development.”
The ad says“7+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below).”
The ad says“Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level.”
The ad says“Solid understanding of low-power design techniques and power-aware physical implementation.”
The ad says“Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.”
The ad says“Proficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development.”
The ad says“Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.”
The ad says“Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.”
The ad says“Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.”
The ad says“Proficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development.”
The ad says“Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level.”

Job Description

Key Responsibilities

Lead MCU/subsystem/block-level closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation.
Collaborate closely with SoC-level teams to align on clocking and floor planning strategies, leveraging strong understanding of SoC methodologies without direct ownership of SoC-level activities.
Work on the different power domains and implement UPF.
Apply knowledge of clocking methodologies to ensure subsystem clock domain integration aligns with overall SoC clock architecture.
Develop and refine subsystem closure methodologies and automation flows to improve design quality and efficiency.
Mentor and guide physical design engineers within the subsystem teams, promoting best practices and methodology adoption.
Work cross-functionally with RTL designers, STA, power, verification, and backend teams to ensure smooth subsystem integration and closure.
Proactively identify and mitigate physical design risks, coordinating with SoC teams on potential impacts and solutions.

Qualifications

Education :M.Tech/ B.Tech in Electrical Engineering
7+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below).
Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level.
Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them.
Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.
Proficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development.
Deep knowledge of SoC design flows with proven ability to work closely with timing closure, power integrity, clocking, verification.
Solid understanding of low-power design techniques and power-aware physical implementation.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.

With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’

At Renesas, you can:

Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.

Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure.

Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.

Are you ready to own your success and make your mark?

Join Renesas. Let’s Shape the Future together.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.