The ad says“Advanced packaging knowledge: 2.5D, 3D, organic substrate”
The ad says“Hands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)”
The ad says“Advanced CDC design, link training protocols, elastic buffer architectures”
The ad says“SerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experience”
The ad says“Deep expertise in D2D PHY, DDR PHY, or SerDes digital design”
The ad says“Strong understanding of UCIe or other high-speed interfaces like DDR/Serdes”
The ad says“Deep expertise in D2D PHY, DDR PHY, or SerDes digital design”
The ad says“DDR4/DDR5/LPDDR PHY or DFI interface experience”
The ad says“DDR4/DDR5/LPDDR PHY or DFI interface experience”
The ad says“Advanced CDC design, link training protocols, elastic buffer architectures”
The ad says“Hands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)”
The ad says“Advanced CDC design, link training protocols, elastic buffer architectures”
The ad says“SerDes digital control (TX/RX equalization, CDR), PCIe PHY, or CXL PHY experience”
The ad says“Python/Perl/Tcl scripting for design automation”
The ad says“Python/Perl/Tcl scripting for design automation”
The ad says“Write RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskew”
The ad says“Experience with SDC constraints, UPF, STA methodology”
The ad says“Strong understanding of UCIe or other high-speed interfaces like DDR/Serdes”
The ad says“Deep expertise in D2D PHY, DDR PHY, or SerDes digital design”
The ad says“Experience with SDC constraints, UPF, STA methodology”
The ad says“Hands-on with synthesis tools (Synopsys DC/Fusion Compiler or Cadence Genus)”
The ad says“Expert SystemVerilog RTL design with strong synthesis optimization skills”
The ad says“Expert SystemVerilog RTL design with strong synthesis optimization skills”
The ad says“Python/Perl/Tcl scripting for design automation”
The ad says“Strong understanding of UCIe or other high-speed interfaces like DDR/Serdes”
The ad says“Experience with SDC constraints, UPF, STA methodology”
Join the leading chiplet startup
As an Eliyan Staff Digital Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility
In this role you will lead the frontend design of our D2D PHY - the core tech behind NuLink, our chiplet interconnect platform
You’ll own the digital PHY from microarchitecture through synthesis, working closely with our architecture, analog, verification, and physical design teams
This is a hands-on technical leadership role
You’ll define PHY architecture, write RTL, optimize for synthesis, create timing constraints, develop firmware sequences, and ensure clean integration across the stack
Your work directly enables next-gen chiplet-based AI and HPC systems
We offer a fun work environment with excellent benefits
Own D2D PHY digital design from microarchitecture definition through synthesis and PD handoff
Design data path and clocking architecture for UCIe-compliant advanced package PHY
Write RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskew
Create microarchitecture specs with power analysis, latency metrics, and performance characterization
Make architectural trade-offs balancing performance, power, area, and timing
