Asks for

The ad says“Demonstrated experience with at least two of the following CPU architectures: AMD (AGESA, EPYC/Ryzen), Intel (FSP, Core/Xeon), or ARM (TF-A, EDK2).”
The ad says“Demonstrated experience with at least two of the following CPU architectures: AMD (AGESA, EPYC/Ryzen), Intel (FSP, Core/Xeon), or ARM (TF-A, EDK2).”
The ad says“Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation.”
The ad says“3+ years of hands-on experience in BIOS/UEFI firmware development or validation.”
The ad says“Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation.”
The ad says“Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation.”
The ad says“Strong understanding of DDR5 memory architecture, training algorithms, SPD/MR registers, and RAS features.”
The ad says“Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.”
The ad says“Experience reading and interpreting hardware schematics, datasheets, and silicon vendor documentation.”
The ad says“Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.”
The ad says“Demonstrated experience with at least two of the following CPU architectures: AMD (AGESA, EPYC/Ryzen), Intel (FSP, Core/Xeon), or ARM (TF-A, EDK2).”
The ad says“Familiarity with hardware debug tools: JTAG debuggers (Intel ITP, Lauterbach), protocol analyzers, oscilloscopes, and serial console interfaces.”
The ad says“Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.”
The ad says“Familiarity with hardware debug tools: JTAG debuggers (Intel ITP, Lauterbach), protocol analyzers, oscilloscopes, and serial console interfaces.”
The ad says“Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.”
The ad says“Familiarity with hardware debug tools: JTAG debuggers (Intel ITP, Lauterbach), protocol analyzers, oscilloscopes, and serial console interfaces.”
The ad says“Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation.”
The ad says“Familiarity with hardware debug tools: JTAG debuggers (Intel ITP, Lauterbach), protocol analyzers, oscilloscopes, and serial console interfaces.”
The ad says“Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.”
The ad says“Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.”
The ad says“Experience with UEFI/EDK2 framework, SMM, DXE, PEI driver development, and ACPI/ASL.”
The ad says“Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.”

Values

The ad says“Understanding of power management frameworks: ACPI, AMD STAPM, Intel DPTF, and platform telemetry.”
The ad says“Experience with version control systems (Git), CI/CD pipelines, and agile engineering workflows.”
The ad says“Experience with AMD PSP, Intel ME/CSME, or ARM TrustZone security subsystems.”
The ad says“Understanding of power management frameworks: ACPI, AMD STAPM, Intel DPTF, and platform telemetry.”
The ad says“Experience with AMD PSP, Intel ME/CSME, or ARM TrustZone security subsystems.”
The ad says“Familiarity with BMC firmware (OpenBMC) and IPMI/Redfish management interfaces.”
The ad says“Experience with version control systems (Git), CI/CD pipelines, and agile engineering workflows.”
The ad says“Exposure to PCIe Gen 5 or CXL 2.0/3.0 interconnect validation.”
The ad says“Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, and machine check architecture (MCA).”
The ad says“Experience with version control systems (Git), CI/CD pipelines, and agile engineering workflows.”
The ad says“Understanding of power management frameworks: ACPI, AMD STAPM, Intel DPTF, and platform telemetry.”
The ad says“Experience with AMD PSP, Intel ME/CSME, or ARM TrustZone security subsystems.”
The ad says“Familiarity with BMC firmware (OpenBMC) and IPMI/Redfish management interfaces.”
The ad says“Hands-on experience with JEDEC DDR5 compliance testing and memory timing optimization.”
The ad says“Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, and machine check architecture (MCA).”
The ad says“Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, and machine check architecture (MCA).”
The ad says“Hands-on experience with JEDEC DDR5 compliance testing and memory timing optimization.”
The ad says“Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, and machine check architecture (MCA).”
The ad says“Exposure to PCIe Gen 5 or CXL 2.0/3.0 interconnect validation.”

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world ---come join our team and see how YOU can make a difference.

Job Description:

We are seeking a skilled and motivated Senior BIOS Engineer to join our system engineering team. In this role, you will work closely with Systems Engineers to troubleshoot, validate, and optimize firmware and low-level software across a diverse portfolio of platforms built on AMD, Intel, and ARM-based CPUs, with a focus on DDR memory subsystems and other critical components. You will play a key role in bringing up/troubleshooting and validating memory subsystem/components on different platforms, resolving complex hardware-software interface issues, and ensuring robust interoperability/compatibility of subsystems/components and production readiness.

Key Responsibilities

Lead BIOS-level bring-up and validation for new hardware platforms, including debug of CPU, chipset, and memory (DDR5/6) subsystems.
Develop and execute validation test plans for BIOS features, power management (ACPI/S-states), security features (Secure Boot, TPM, AMD PSP, Intel TXT/SGX), and boot flows.
Support manufacturing and sustaining engineering with BIOS customization, factory programming, and field issue resolution.
Analyze, troubleshoot, and customize BIOS/UEFI firmware for platforms using AMD EPYC/Ryzen, Intel Core/Xeon, and ARM-based processors.
Collaborate closely with Systems Engineers to troubleshoot and validate subsystems and components across the full platform stack.
Analyze and resolve hardware-firmware interface issues including POST failures, memory training errors, PCIe enumeration problems, and thermal/power sequencing anomalies.
Configure and validate DDR5 memory subsystems, including SPD/XMP programming, memory training tuning, RAS features, and JEDEC compliance.
Work with CPU vendors to ensure the adoption of certain BIOS customization for certain platforms
Debug using industry-standard tools such as JTAG/ITP debuggers, logic analyzers, oscilloscopes, and serial console output.
Author and maintain issue logs/notes, validation reports, debug guides, and internal technical documentation.
Participate in design reviews, hardware bring-up planning, and cross-functional meetings

Required Qualifications

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
3+ years of hands-on experience in BIOS/UEFI firmware development or validation.
Demonstrated experience with at least two of the following CPU architectures: AMD (AGESA, EPYC/Ryzen), Intel (FSP, Core/Xeon), or ARM (TF-A, EDK2).
Strong understanding of DDR5 memory architecture, training algorithms, SPD/MR registers, and RAS features.
Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation.
Experience with UEFI/EDK2 framework, SMM, DXE, PEI driver development, and ACPI/ASL.
Familiarity with hardware debug tools: JTAG debuggers (Intel ITP, Lauterbach), protocol analyzers, oscilloscopes, and serial console interfaces.
Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO.
Experience reading and interpreting hardware schematics, datasheets, and silicon vendor documentation.
Excellent analytical and problem-solving skills with the ability to work across hardware and software boundaries.
Strong written and verbal communication skills; experience authoring technical documentation.

Preferred Qualifications

Experience with AMD PSP, Intel ME/CSME, or ARM TrustZone security subsystems.
Familiarity with BMC firmware (OpenBMC) and IPMI/Redfish management interfaces.
Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, and machine check architecture (MCA).
Exposure to PCIe Gen 5 or CXL 2.0/3.0 interconnect validation.
Hands-on experience with JEDEC DDR5 compliance testing and memory timing optimization.
Understanding of power management frameworks: ACPI, AMD STAPM, Intel DPTF, and platform telemetry.
Prior collaboration with silicon vendors (AMD, Intel, Arm Ltd.) on pre-silicon or early-silicon bring-up.
Experience with version control systems (Git), CI/CD pipelines, and agile engineering workflows.

Work Environment & Collaboration

This role requires close day-to-day collaboration with Systems Engineers, Hardware Engineers, and Design/Applications Engineers in a fast-paced lab environment. You will have access to pre-production hardware, silicon support, and a dedicated debug lab equipped with industry-standard instrumentation. Occasional travel to vendor or customer sites may be required.

What We Offer

Competitive salary and equity compensation.
Comprehensive health, dental, and vision benefits.
Opportunity to work on cutting-edge hardware with next-generation silicon.
Collaborative, technically rigorous team culture.
Flexible work arrangements and professional development support.

MPS offers a comprehensive benefits package. We provide health care coverage, dental and vision, 401(K) with a company match, Employee Stock Purchase Program (ESPP), up to 11 company paid holidays, and 15- 20 days of paid time off depending on your tenure, generous discretionary company bonuses, and life and disability protection. Employees in sales positions may be eligible for our sales incentive bonuses. Employees in certain positions may be eligible for stock compensation. For more information on MPS’ benefits please view our company website at www.monolithicpower.com.

Pay is based on market location and may vary based on factors including experience, skills, education and other job-related reasons. The base salary range for this position in California is $140,000 - $220,000.

Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.