Asks for

The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“This role is ideal for a senior low-power SoC architect who enjoys hands-on analysis, silicon debug, architecture specification, automation, and customer-facing technical influence.”
The ad says“Experience with Arm Cortex-A, RISC-V, DSP, or heterogeneous multicore architectures.”
The ad says“Arm Cortex-M architecture experience.”
The ad says“This role is ideal for a senior low-power SoC architect who enjoys hands-on analysis, silicon debug, architecture specification, automation, and customer-facing technical influence.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Experience with Cadence Genus or equivalent industry power analysis tooling (Cadence Joules, Synopsys PrimePower, Siemens PowerPro).”
The ad says“Experience with Cadence Genus or equivalent industry power analysis tooling (Cadence Joules, Synopsys PrimePower, Siemens PowerPro).”
The ad says“Familiarity with AI-assisted engineering environments such as Claude Code, Cursor, or equivalent.”
The ad says“Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git.”
The ad says“Familiarity with AI-assisted engineering environments such as Claude Code, Cursor, or equivalent.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Experience with Arm Cortex-A, RISC-V, DSP, or heterogeneous multicore architectures.”
The ad says“Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Ambiq is looking for a Sr. Staff SOC Power & Performance Architect to help shape the architecture behind some of the industry’s most power-efficient SoCs. You will drive power and performance analysis, budgeting, modeling, and debug from early architecture through silicon correlation, while defining practical architecture guidance for power management, clocking/reset, fabric, and embedded system behavior.”
The ad says“Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.”
The ad says“Develop and automate power modeling infrastructure, reporting flows, regression dashboards, and analysis tooling using Python and/or TCL.”
The ad says“Experience with Arm Cortex-A, RISC-V, DSP, or heterogeneous multicore architectures.”
The ad says“Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git.”
The ad says“Experience with Cadence Genus or equivalent industry power analysis tooling (Cadence Joules, Synopsys PrimePower, Siemens PowerPro).”
The ad says“This role is ideal for a senior low-power SoC architect who enjoys hands-on analysis, silicon debug, architecture specification, automation, and customer-facing technical influence.”
The ad says“Experience with Cadence Genus or equivalent industry power analysis tooling (Cadence Joules, Synopsys PrimePower, Siemens PowerPro).”
The ad says“Develop and automate power modeling infrastructure, reporting flows, regression dashboards, and analysis tooling using Python and/or TCL.”
The ad says“UPF / IEEE 1801 authoring or review experience.”

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

Ambiq is looking for a Sr. Staff SOC Power & Performance Architect to help shape the architecture behind some of the industry’s most power-efficient SoCs. You will drive power and performance analysis, budgeting, modeling, and debug from early architecture through silicon correlation, while defining practical architecture guidance for power management, clocking/reset, fabric, and embedded system behavior.

This role is ideal for a senior low-power SoC architect who enjoys hands-on analysis, silicon debug, architecture specification, automation, and customer-facing technical influence.

Responsibilities

Execute power and performance analysis across pre-silicon modeling, RTL power analysis, power-aware simulation, and post-silicon correlation.
Build and maintain SoC, subsystem, and use-case-level power budgets.
Drive variance analysis against power and performance targets, surfacing risks early.
Lead architectural debug of power anomalies in simulation, emulation, or silicon.
Trace issues from waveform to RTL to architectural intent to root cause.
Develop and automate power modeling infrastructure, reporting flows, regression dashboards, and analysis tooling using Python and/or TCL.
Characterize power states, transitions, leakage/dynamic splits, Vmin behavior, retention, and corner behavior on first silicon.
Feed silicon learnings back into next-generation architecture.
Contribute architecture and microarchitecture specifications for power management, clocking/reset, fabric, flow sequencing, software/hardware interaction, and power models.
Analyze process-node tradeoffs and translate them into architectural recommendations.
Support use-case and test-case development.
Partner with physical design on power domain partitioning and UPF/power intent mapping.
Work with software architecture teams to define power management flows, APIs, and power manager behavior.
Support FPGA teams during early bring-up of power management and global flows.
Translate silicon power/performance capabilities into datasheet guidance, competitive positioning, and customer-facing collateral.
Support pre-sales, field engineering, RFQ/RFI responses, customer meetings, and customer use-case power estimation as Ambiq’s P&P subject-matter expert.

Qualifications

BS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
7+ years of architecture experience in low-power SoC, embedded SoC, semiconductor, MCU, processor, or related silicon environments.
Hands-on ownership of power and/or performance analysis, budgeting, and debug.
Experience with Cadence Genus or equivalent industry power analysis tooling (Cadence Joules, Synopsys PrimePower, Siemens PowerPro).
Experience with power-aware simulation flows.
Strong Python and/or TCL scripting for modeling, automation, reporting, and analysis.
Demonstrated ability to write architecture and microarchitecture specifications that engineering teams can build from.
Strong written and verbal communication skills.
Ability to work effectively across hardware, software, physical design, validation, applications, field, marketing, and sales teams.
Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git.

Preferred Qualifications

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
10+ years of semiconductor or embedded SoC industry experience.
UPF / IEEE 1801 authoring or review experience.
Clocking/reset architecture experience.
Arm Cortex-M architecture experience.
Experience with Arm Cortex-A, RISC-V, DSP, or heterogeneous multicore architectures.
Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.
Prior customer-facing, pre-sales, field, or applications engineering engagement.
Familiarity with AI-assisted engineering environments such as Claude Code, Cursor, or equivalent.

Must be currently authorized to work in the United States for any employer. This role will be onsite 5 days a week in Austin, TX office.