Asks for

The ad says“Demonstrated ability to perform competitive analysis, including interpreting teardown data, benchmarking memory bandwidth/latency, and drawing clear architectural conclusions and recommendations.”
The ad says“Demonstrated ability to perform competitive analysis, including interpreting teardown data, benchmarking memory bandwidth/latency, and drawing clear architectural conclusions and recommendations.”
The ad says“18+ years of experience in DRAM / memory subsystem architecture, SoC or memory controller design, or closely related roles in semiconductor or system companies. Deep understanding of modern DRAM technologies (e.g., DDR, LPDDR, GDDR, HBM) and non‑volatile memories (e.g., NAND flash, managed NAND/SSD), including key tradeoffs in bandwidth, latency, power, capacity, packaging, and reliability.”
The ad says“18+ years of experience in DRAM / memory subsystem architecture, SoC or memory controller design, or closely related roles in semiconductor or system companies. Deep understanding of modern DRAM technologies (e.g., DDR, LPDDR, GDDR, HBM) and non‑volatile memories (e.g., NAND flash, managed NAND/SSD), including key tradeoffs in bandwidth, latency, power, capacity, packaging, and reliability.”
The ad says“18+ years of experience in DRAM / memory subsystem architecture, SoC or memory controller design, or closely related roles in semiconductor or system companies. Deep understanding of modern DRAM technologies (e.g., DDR, LPDDR, GDDR, HBM) and non‑volatile memories (e.g., NAND flash, managed NAND/SSD), including key tradeoffs in bandwidth, latency, power, capacity, packaging, and reliability.”
The ad says“Proven experience working directly with memory vendors on product definition, bring‑up, or co‑development, and familiarity with how large‑scale customers influence vendor roadmaps.”
The ad says“Solid background in SoC and system memory subsystems, including memory controllers, PHYs, signal integrity, power delivery, and how memory choices impact overall SoC and platform performance and power.”
The ad says“18+ years of experience in DRAM / memory subsystem architecture, SoC or memory controller design, or closely related roles in semiconductor or system companies. Deep understanding of modern DRAM technologies (e.g., DDR, LPDDR, GDDR, HBM) and non‑volatile memories (e.g., NAND flash, managed NAND/SSD), including key tradeoffs in bandwidth, latency, power, capacity, packaging, and reliability.”

NVIDIA’s SoC Product Architecture team defines the platforms that power AI, graphics, and accelerated computing across data center, automotive, client, and edge products. As a Senior SoC Product Architect, Memory Ecosystem, you will drive NVIDIA’s external memory ecosystem across DRAM and non‑volatile flash, working with major memory vendors to align roadmaps, co‑innovate new technologies, and ensure our SoC portfolio delivers industry‑leading bandwidth, latency, power, and cost.

What you’ll be doing:

Partner with all major memory vendors to understand their technology and product roadmaps (e.g., DDR/LPDDR, GDDR, HBM, NAND, emerging NVM) and align them with NVIDIA’s SoC and platform roadmaps.
Steer vendor roadmaps by articulating NVIDIA’s performance, power, capacity, form‑factor, and reliability requirements, translating SoC and system needs into clear, data‑driven feedback and requests.
Innovate new DRAM solutions in collaboration with vendors, exploring novel architectures, signaling, packaging, and power‑management techniques to meet the bandwidth, latency, and power requirements of future NVIDIA SoCs and systems.
Work closely with SoC architects, memory controller designers, and board/system teams to co‑optimize SoC + memory subsystem architecture, including channel topologies, speed grades, rank/stack configurations, and error‑management strategies.
Represent NVIDIA at regular vendor technical reviews and key technical/roadmap meetings, presenting consolidated SoC roadmap needs, performance data, and proposals, and driving clear follow‑ups and decisions.
Collaborate with sourcing, operations, substrate and PCB design, and quality teams to factor supply, cost, and reliability considerations into memory technology choices and long‑term ecosystem strategy.

What we need to see:

MS in Electrical Engineering, Computer Engineering, Physics, or related field, or equivalent experience.
18+ years of experience in DRAM / memory subsystem architecture, SoC or memory controller design, or closely related roles in semiconductor or system companies. Deep understanding of modern DRAM technologies (e.g., DDR, LPDDR, GDDR, HBM) and non‑volatile memories (e.g., NAND flash, managed NAND/SSD), including key tradeoffs in bandwidth, latency, power, capacity, packaging, and reliability.
Proven experience working directly with memory vendors on product definition, bring‑up, or co‑development, and familiarity with how large‑scale customers influence vendor roadmaps.
Solid background in SoC and system memory subsystems, including memory controllers, PHYs, signal integrity, power delivery, and how memory choices impact overall SoC and platform performance and power.
Demonstrated ability to perform competitive analysis, including interpreting teardown data, benchmarking memory bandwidth/latency, and drawing clear architectural conclusions and recommendations.
Strong communication and presentation skills, with experience representing technical positions in vendor meetings, technical reviews, and multi-functional internal reviews. Ability to work across functions (architecture, design, systems, sourcing, operations) and regions, driving alignment and decisions without direct authority.

Ways to stand out from the crowd:

Direct experience defining or architecting HBM, GDDR, or high‑speed LPDDR solutions for GPUs, AI accelerators, or high‑performance SoCs.
Hands‑on work with advanced packaging (e.g., 2.5D/3D, CoWoS, multi‑chip modules) involving high‑bandwidth memory interfaces.
Prior ownership of memory‑related driven teardowns or benchmarking programs, with clear examples of how results influenced product or technology direction.
Established relationships with major memory vendors and a history of successful roadmap or co‑development engagements.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward‑thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 320,000 USD - 488,750 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 7, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Asks for

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