Asks for

The ad says“Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference.”
The ad says“Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).”
The ad says“Solid understanding of chip packaging.”
The ad says“In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.”
The ad says“In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.”
The ad says“In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.”
The ad says“Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).”
The ad says“Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).”
The ad says“Solid Knowledge in signal processing, communication system.”
The ad says“Minimum of 12 years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.”
The ad says“At least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).”
The ad says“At least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).”
The ad says“At least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).”
The ad says“Strong knowledge of pad ring placement and ESD strategy.”
The ad says“Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.”
The ad says“Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.”
The ad says“Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.”
The ad says“Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.”
The ad says“Hands-on experience with IP selection to meet the specific needs of the design.”
The ad says“Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.”
The ad says“Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.”
The ad says“Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).”
The ad says“Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).”
The ad says“Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).”
The ad says“Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).”
The ad says“Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).”
The ad says“Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.”
The ad says“Strong knowledge of pad ring placement and ESD strategy.”
The ad says“Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).”
The ad says“Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).”
The ad says“Experienced with silicon bring-up, validation, and post-silicon debug methodologies.”
The ad says“Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.”
The ad says“Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).”
The ad says“Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.”
The ad says“Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.”
The ad says“In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.”
The ad says“Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference.”
The ad says“Exposure to all aspects of RFIC system design.”
The ad says“Minimum of 12 years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.”
The ad says“Minimum of 12 years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.”
The ad says“Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.”
The ad says“Solid Knowledge in signal processing, communication system.”
The ad says“Experienced with silicon bring-up, validation, and post-silicon debug methodologies.”
The ad says“At least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).”
The ad says“Experienced with silicon bring-up, validation, and post-silicon debug methodologies.”

Join our cutting-edge start-up adventure!

Who are we?

Join the Revolution in GNSS and IoT Connectivity

At Qualinx, we’re not just building chips, we’re engineering the future fabric of the connected world. As a pioneering semiconductor scale-up, we’re transforming how devices connect, communicate, and operate through our ground-breaking Digital RF technology. Our mission goes beyond ultra-low power GNSS: we’re redefining what’s possible in adaptive, scalable, and intelligent connectivity for the Internet of Things.

Born from deep-tech innovation at TU Delft, our team of visionary engineers and bold thinkers is tackling the toughest challenges in GNSS and IoT, starting with power consumption and expanding into dynamic, context-aware solutions that adapt to any environment or use case. We’ve already achieved what many thought impossible: the world’s most advanced GNSS chipset. But that’s just the beginning.

At Qualinx, we believe that the future of connectivity lies in precision, efficiency, and adaptability. Our ambition is to become the invisible thread that seamlessly interconnects billions of devices: powering a smarter, more responsive world.

What Sets Us Apart

Joining Qualinx is about becoming part of a culture that’s as ambitious as it is authentic. We hold ourselves to high standards, thrive on solving the unexpected, and push boundaries together. But we also know how to enjoy the ride. Our culture is a unique blend of curiosity, team spirit, and a touch of unconventional charm. It’s fast-paced, fun, and grounded in a sober sense of purpose and perspective. Whether we’re deep in design reviews or sharing laughs over lunch, we’re building something meaningful together. At Qualinx, you’re not just contributing to a ground-breaking technology, you’re helping shape a team that’s redefining what it means to work in deep tech.

Job Description

Key Responsibilities

System Design & Integration: You will be responsible for defining the high-level architecture of the SoC, determining which components will be included on the chip.
You will collaborate with the hardware design teams to guide the implementation of the chip's physical design.
You will coordinate with our firmware & GNSS team to ensure the SoC Architecture supports efficient execution of software, including drivers, operating systems and applications.
You will define and implement security features to protect the SoC from vulnerabilities.
You will keep up with the advances in the semiconductor industry and make sure the SoC architecture remains scalable and adaptable for future generations of products.
Managing product timelines and deliverables, making sure that the SoC Development follows the planned schedule and stays within budget.

Requirements

Qualinx is looking for a result-driven and conscientious senior SoC Architect. Someone who thrives in an environment where your proactive and can-do attitude is highly appreciated. The ideal candidate for this role must have:

Minimum of 12 years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.
Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).
At least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).
Solid understanding of chip packaging.
Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.
Strong problem-solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.
Experienced with silicon bring-up, validation, and post-silicon debug methodologies.
Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.
Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).
Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference.
Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).
Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.
Hands-on experience with IP selection to meet the specific needs of the design.
Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.
Strong knowledge of pad ring placement and ESD strategy.
In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.
Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.
Solid Knowledge in signal processing, communication system.
Exposure to all aspects of RFIC system design.

What's in it for you?

At Qualinx, we believe that great work starts with a great environment, pioneering technology and a fun dynamic market to address. Here’s what you can expect when you join our team:

Ownership and Impact: We offer employee equity, giving you the opportunity to share in the success you help create.
Well-being Matters: Your physical and mental health are important to us. We provide access to wellness resources, including company discounts and a free mental healthcare platform.
Global Talent, Local Support: If you're relocating from abroad, we provide full support throughout the visa process to ensure a smooth transition.
Future-Focused Benefits: We contribute to your pension savings to help you plan ahead with confidence.

Inspiring Workspace: Work from a modern and vibrant, well-equipped office designed to help you do your best work.

Scale-up Team Spirit: We celebrate our wins together with fun quarterly events—think great food, games, and unforgettable experiences.