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Senior Staff Engineer, Physical Implementation CAD Lead at Samsung Electronics America, Inc. · Katori

Asks for

The ad says“Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.”
The ad says“Strong understanding of advanced technology node challenges (<5nm), including physical verification flows (Calibre/ICV) and DTCO considerations.”
The ad says“Strong understanding of advanced technology node challenges (<5nm), including physical verification flows (Calibre/ICV) and DTCO considerations.”
The ad says“Strong understanding of advanced technology node challenges (<5nm), including physical verification flows (Calibre/ICV) and DTCO considerations.”
The ad says“11+ years of hands-on experience in Physical Design CAD, methodology development, or design enablement for complex GPU, CPU, or SoC programs.”
The ad says“Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.”
The ad says“Strong understanding of advanced technology node challenges (<5nm), including physical verification flows (Calibre/ICV) and DTCO considerations.”
The ad says“Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.”
The ad says“Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.”
The ad says“Proficiency in scripting and automation (Python, Tcl, shell) with experience building scalable CAD infrastructure.”
The ad says“Proficiency in scripting and automation (Python, Tcl, shell) with experience building scalable CAD infrastructure.”
The ad says“Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.”
The ad says“Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.”
The ad says“Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.”
The ad says“Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.”
The ad says“Proficiency in scripting and automation (Python, Tcl, shell) with experience building scalable CAD infrastructure.”
The ad says“Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.”
The ad says“Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.”
The ad says“Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.”

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Senior Staff Physical Implementation CAD Engineer, you will shape the development and deployment of physical design CAD flows and methodologies to enable high-performance, power-efficient GPU and SoC designs at advanced technology nodes.

In this high-impact individual contributor role, you will lead a team of engineers focusing on physical implementation methodology innovation, while driving automation and scalable infrastructure across concurrent programs. You bring strong expertise in P&R tool ecosystems, bleeding-edge node challenges (<5nm), and cross-functional collaboration to improve flow robustness, design productivity, and PPA outcomes across Samsung’s next-generation silicon.

Leveraging your expertise in physical design and CAD methodology, you define and evolve next-generation physical design flows (synthesis, placement, routing, timing, and power optimization) to enable scalable, high-quality design execution across advanced nodes.
You provide technical leadership and hands-on support to project teams, driving flow triage, adapting methodologies to program-specific needs, and resolving complex implementation challenges through data-driven analysis.
You champion automation and infrastructure development, building robust scripting and tool integrations (Python, Tcl, shell) while advancing AI-assisted methodologies to improve predictability, turnaround time, and engineering efficiency.
You advance cross-functional collaboration with internal design and DTCO teams, and external EDA vendor partners to evaluate emerging technologies, influence tool capabilities, and proactively address new challenges introduced by sub-5nm process nodes.
You inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation-driven execution, and staying ahead of emerging GPU physical implementation methodology and CAD best practices.

Skills and Qualifications

11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
11+ years of hands-on experience in Physical Design CAD, methodology development, or design enablement for complex GPU, CPU, or SoC programs.
Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.
Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.
Strong understanding of advanced technology node challenges (<5nm), including physical verification flows (Calibre/ICV) and DTCO considerations.
Proficiency in scripting and automation (Python, Tcl, shell) with experience building scalable CAD infrastructure.
Experience with leading complex technical initiatives, driving process and methodology innovation, and mentoring engineers.
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence in a fast-paced, global environment.

Our Team

The Advanced Design Technology and Design Implementation teams play a critical role in driving technology development across Samsung System LSI business. Operating at the intersection of design technology and physical implementation, we engage with Foundry partners from early-phase technology exploration through the full design lifecycle. Our teams span advanced design process and methodology development, GPU physical design and implementation, CAD, and DTCO—accelerating adoption of advanced technology nodes and enabling market-differentiating power, performance, and area (PPA), silicon reliability, and design turnaround time for GPU and system-level IP solutions.

You will join a diverse, highly collaborative organization working across concurrent-development cycles, with direct impact on consumer technologies used worldwide. Here you’ll help build what’s next, experiment with new ideas and explore different GPU development verticals, broaden technical expertise, and solve impactful challenges in a supportive environment that values collaboration, continuous learning, and growth.

Total Rewards

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $297,200. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

Trade Secrets

By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

U.S. Export Control

This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

#SARC #ACL

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