Asks for

The ad says“Experience with architecture specification and requirements management tooling for authoring and maintaining the PRD and tracing it back to the MRD; UCIe, PCIe, and Ethernet protocol/standards documentation and compliance tooling; architecture and performance modeling tools, including custom or commercial full-chip performance/power models; Python / C++ for modeling, scripting, and analysis; and collaboration and documentation platforms for coordinating input from analog, photonics, packaging, memory, and other subsystem architects into a single PRD.”
The ad says“Strong digital subsystem and interconnect fabric architecture experience, including defining on-chip interconnect and digital subsystem partitioning for a complex SoC.”
The ad says“Deep, hands-on high-speed I/O subsystem expertise, particularly high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol requirements shape physical-layer architecture.”
The ad says“Deep, hands-on high-speed I/O subsystem expertise, particularly high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol requirements shape physical-layer architecture.”
The ad says“Strong digital subsystem and interconnect fabric architecture experience, including defining on-chip interconnect and digital subsystem partitioning for a complex SoC.”
The ad says“Deep, hands-on high-speed I/O subsystem expertise, particularly high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol requirements shape physical-layer architecture.”
The ad says“Experience translating marketing/product-level requirements into precise, engineering-actionable architecture specifications and reasoning about full-chip performance, power, and area (PPA) trade-offs.”
The ad says“Experience with architecture specification and requirements management tooling for authoring and maintaining the PRD and tracing it back to the MRD; UCIe, PCIe, and Ethernet protocol/standards documentation and compliance tooling; architecture and performance modeling tools, including custom or commercial full-chip performance/power models; Python / C++ for modeling, scripting, and analysis; and collaboration and documentation platforms for coordinating input from analog, photonics, packaging, memory, and other subsystem architects into a single PRD.”
The ad says“Deep, hands-on high-speed I/O subsystem expertise, particularly high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol requirements shape physical-layer architecture.”
The ad says“7–10 years of experience in SoC or product architecture roles, with proven SoC/product architecture ownership and demonstrated experience taking a product from MRD-level requirements through a complete, implementable PRD-level architecture covering multiple subsystems and at least one full product architecture cycle.”
The ad says“Deep, hands-on high-speed I/O subsystem expertise, particularly high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol requirements shape physical-layer architecture.”

About us

We see the semiconductor industry as a realm of possibility. We see opportunity. We see the profound impact that our graphene solutions will have in transforming the industry. We invite you to join us in driving change with our fundamentally human-centered approach, uniting bright minds around a shared vision. The vision is: Prove to everybody that you can make a fundamental change. Prove with your knowledge and skills how things can be done differently. Together, we can change the paradigm of how the world connects

About our technology

The semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology. We connect chips to high-throughput, low-delay computing networks. The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one. Our graphene photonic innovation increases computing power and efficiency to a new order of magnitude

In short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution

The Role

We are seeking a skilled Senior SoC Architect at Black Semiconductor to drive the architecture of our entire Electronics-Photonics IC (EPIC) SoC, translating the Marketing Requirement Document (MRD) into a complete, internally consistent, and implementable Product Requirement Document (PRD) covering digital, analog, I/O, and memory subsystems.

You will own the digital and high-speed I/O subsystem architecture directly, with particular depth in high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet. Working closely with the Analog/RF System Architect, Photonics System Architect, Package Electrical/SI Architect, memory subsystem owner, product management, and engineering teams, you will integrate their subsystem architectures into one coherent overall product architecture.

To join our team, you should be excited to

Own the overall EPIC SoC technical leadership from initial concept through production and drive cross-functional technical alignment across photonics, analog, digital, technology, and product teams.
Build and document the overall product architecture, translating the MRD into a complete PRD and ensuring architectural decisions, technical requirements, dependencies, and trade-offs are consistently aligned across teams.
Own the digital subsystem architecture, including core logic, on-chip interconnect fabric, and subsystem partitioning.
Own the high-speed I/O subsystem architecture, with particular depth in high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol layers map onto the physical SerDes implementation.
Partner with the Analog/RF System Architect, Photonics System Architect, Package Electrical/SI Architect, and memory subsystem owner to integrate their architectures and ensure the full-chip architecture is internally consistent and feasible within the target electrical, physical, and packaging constraints.
Drive full-chip performance, power, and area (PPA) trade-off analysis, partner with external vendors/3rd-party IP providers on full-chip validation and characterization teams on product characterization, and make the calls needed to keep the PRD internally consistent.
Present the integrated architecture and PRD to product management and engineering leadership and own it through to sign-off.

Your Qualifications

Essential

7–10 years of experience in SoC or product architecture roles, with proven SoC/product architecture ownership and demonstrated experience taking a product from MRD-level requirements through a complete, implementable PRD-level architecture covering multiple subsystems and at least one full product architecture cycle.
Deep, hands-on high-speed I/O subsystem expertise, particularly high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol requirements shape physical-layer architecture.
Strong digital subsystem and interconnect fabric architecture experience, including defining on-chip interconnect and digital subsystem partitioning for a complex SoC.
Strong cross-domain integration skills, with the ability to take analog, photonic, packaging, and memory architecture input from peer subsystem owners and integrate it into one internally consistent PRD without needing to personally own those domains.
Experience translating marketing/product-level requirements into precise, engineering-actionable architecture specifications and reasoning about full-chip performance, power, and area (PPA) trade-offs.
Experience with 3rd-party IP vendors, including evaluating and selecting external IPs and design integration partners.
Experience with architecture specification and requirements management tooling for authoring and maintaining the PRD and tracing it back to the MRD; UCIe, PCIe, and Ethernet protocol/standards documentation and compliance tooling; architecture and performance modeling tools, including custom or commercial full-chip performance/power models; Python / C++ for modeling, scripting, and analysis; and collaboration and documentation platforms for coordinating input from analog, photonics, packaging, memory, and other subsystem architects into a single PRD.

Nice to Have

Previous experience serving as an SoC Chief Engineer, with end-to-end accountability for a product's full-chip architecture, schedule, and quality outcomes.
Familiarity with silicon photonics or electro-optic I/O, and how it changes traditional I/O subsystem architecture assumptions.
Familiarity with advanced packaging, including 2.5D/3D and chiplet integration, and its impact on full-chip architecture choices.
Experience working directly with product management and/or customers to shape MRD-level requirements.
Experience with CXL or other die-to-die/coherent interconnect standards adjacent to UCIe/PCIe.

Our work culture

People Over Processes. At Black Semiconductor, flexibility is key—we ensure work adapts to life, not the other way around. We champion work-life harmony, where careers are meaningful and enriching. Our processes are human-centric, allowing you to focus on what matters

Let’s grow together. Your potential is our priority. We provide the autonomy to make a lasting impact and nurture your growth through a culture of continuous learning. We invest in your journey for professional and personal development

Your Health and Future Matter. Your well-being is paramount. We offer a comprehensive benefits package with outstanding insurance, pension and virtual stock options for your mental, physical, and financial health. Your peace of mind is our priority - in the present and future

We Live Openness. Collaboration and inclusivity are the cornerstones of our culture. We practice openness, fostering trust and respect. Individuality is our collective strength, fueling innovation and driving us forward

We connect chips – and people. We encourage qualified individuals from any background to apply. We foster an inclusive and supportive work environment that values collaboration, innovation, and growth. Join our team and be part of an organization dedicated to making a difference in the industry

If your application results in an employment relationship, your Applicant Data will be transferred to our personnel records and processed in accordance with applicable legal requirements; otherwise, your Applicant Data will be retained for up to six (6) months after completion of the recruitment process. Read more about our privacy policy here.

Asks for

Values

Essential

Nice to Have