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Senior Physical Design Methodology Engineer, Innovus Flows at Mellanox Technologies, Ltd. · Katori

Asks for

The ad says“Expertise and in-depth knowledge of industry standard EDA tools and proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++”
The ad says“Experience with power distribution networks, Design for Yield and Manufacturability and thermal management”
The ad says“Solid understanding of EM and IR analysis and closure”
The ad says“Strong background in STA, extraction, timing and RC correlation”
The ad says“Experience in low power design with UPF, and use of FSDB/SAIFs for power optimization”
The ad says“Understanding of synthesis, hierarchical design, pinning and budgeting flows”
The ad says“Solid understanding of EM and IR analysis and closure”
The ad says“Experience in low power design with UPF, and use of FSDB/SAIFs for power optimization”
The ad says“Experience with power distribution networks, Design for Yield and Manufacturability and thermal management”
The ad says“Expertise and in-depth knowledge of industry standard EDA tools and proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++”
The ad says“Minimum 7 years of experience in Physical Design; emphasis on methodology and flow development is highly preferred”
The ad says“Strong understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization”
The ad says“Understanding of synthesis, hierarchical design, pinning and budgeting flows”
The ad says“Experience with power distribution networks, Design for Yield and Manufacturability and thermal management”
The ad says“Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes”
The ad says“Expertise and in-depth knowledge of industry standard EDA tools and proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++”
The ad says“Strong background in STA, extraction, timing and RC correlation”
The ad says“Strong understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization”
The ad says“Strong background in STA, extraction, timing and RC correlation”
The ad says“Understanding of synthesis, hierarchical design, pinning and budgeting flows”
The ad says“Expertise and in-depth knowledge of industry standard EDA tools and proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++”
The ad says“Experience with power distribution networks, Design for Yield and Manufacturability and thermal management”
The ad says“Strong background in STA, extraction, timing and RC correlation”
The ad says“Experience in low power design with UPF, and use of FSDB/SAIFs for power optimization”

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of NVIDIA's products – Datacenter AI, HPC, Networking, Robotics, Autonomous driving, gaming and more. As the cadence of NVIDIA’s chip cycle shortens, it poses new challenges for physical design teams to not only deliver the best PPA on the chips, but to also do it at scale, in the shortest possible time. Your work in physical design methodology directly enables our speed to market in delivering industry’s leading chip hardware. This role provides a unique opportunity to innovate at the cutting edge of process technology, EDA tools, and PD flows through collaboration with RTL, synthesis, DFT, foundry, timing other cross functional teams to push the limits of physical design at scale.

What you'll be doing:

Developing innovative physical design methodologies for implementation of GPU, CPU, Network processors and SOC, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes
Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines
Use AI/ML approaches to CAD to improve design performance and turnaround time, while improving efficiency and productivity of designers

What we need to see:

MS in Electrical or Computer Engineering (or equivalent experience)
Minimum 7 years of experience in Physical Design; emphasis on methodology and flow development is highly preferred
Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes
Strong understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization
Strong background in STA, extraction, timing and RC correlation
Experience in low power design with UPF, and use of FSDB/SAIFs for power optimization
Solid understanding of EM and IR analysis and closure
Understanding of synthesis, hierarchical design, pinning and budgeting flows
Experience with power distribution networks, Design for Yield and Manufacturability and thermal management
Expertise and in-depth knowledge of industry standard EDA tools and proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++

Ways to stand out from the crowd:

Experience applying ML models, LLMs, and agentic AI techniques to EDA/PD problems (analytics, prediction, optimization)
Proficiency with data analysis/ML libraries (e.g., NumPy, SciPy, scikit-learn, PyTorch, etc.)
Proficiency in Cadence EDA tool suite – Innovus/genus/tempus/quantus/joules etc.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. And due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 6, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Asks for

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