Asks for

The ad says“Use Cadence or Synopsys based physical design flows to support implementation, optimisation, and signoff activities.”
The ad says“Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.”
The ad says“Analyse and resolve timing, power, IR/EM, DRC, and LVS issues with guidance from senior engineers where required.”
The ad says“Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.”
The ad says“Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.”
The ad says“Analyse and resolve timing, power, IR/EM, DRC, and LVS issues with guidance from senior engineers where required.”
The ad says“Analyse and resolve timing, power, IR/EM, DRC, and LVS issues with guidance from senior engineers where required.”
The ad says“Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.”
The ad says“Analyse and resolve timing, power, IR/EM, DRC, and LVS issues with guidance from senior engineers where required.”
The ad says“Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.”
The ad says“Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.”
The ad says“Use Cadence or Synopsys based physical design flows to support implementation, optimisation, and signoff activities.”
The ad says“Apply a good working knowledge of synthesis and timing constraints to review implementation results and provide informed feedback to the design team.”
The ad says“Analyse and resolve timing, power, IR/EM, DRC, and LVS issues with guidance from senior engineers where required.”
The ad says“Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.”
The ad says“Apply a good working knowledge of synthesis and timing constraints to review implementation results and provide informed feedback to the design team.”

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Senior Physical Design Engineer

Role Overview

The Senior Physical Design Engineer supports the end-to-end physical implementation and signoff of digital blocks and SoCs. Working as part of a collaborative and potentially geographically distributed engineering team, the role applies practical physical design knowledge to deliver high-quality implementation results while developing technical depth across the RTL-to-GDSII flow.

Key Responsibilities

Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.
Use Cadence or Synopsys based physical design flows to support implementation, optimisation, and signoff activities.
Apply a good working knowledge of synthesis and timing constraints to review implementation results and provide informed feedback to the design team.
Analyse and resolve timing, power, IR/EM, DRC, and LVS issues with guidance from senior engineers where required.
Strong communication, and teamwork skills, with a willingness to learn and take ownership of assigned implementation tasks.

Qualifications

B.Tech., M.Tech., or equivalent qualification in Electrical Engineering, Electronics Engineering, or a related discipline.
Approximately 3–7 years of relevant physical design or digital implementation experience.
Hands-on experience with industry-standard physical design and signoff tools, preferably within a Cadence or Synopsys environment.

#LI-CC1

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days