Asks for

The ad says“Expert-level proficiency in Altium Designer for schematic capture and PCB layout; comfort with rule-driven design, layer stack management, and library administration.”
The ad says“Demonstrated experience designing and laying out power electronics: DC/DC converters, power planes, bus bars/high-current traces, thermal management, and power protection schemes (e.g., fusing, current limiting).”
The ad says“Solid understanding of DFM/DFA principles and hands-on experience working directly with fabrication houses and contract manufacturers.”
The ad says“Practical knowledge of EMC/EMI mitigation techniques in layout (grounding, shielding, plane splits, filtering placement).”
The ad says“Demonstrated experience with high-speed digital layout: impedance-controlled routing, differential pairs, length matching, via optimization, and stack-up design for GHz-class interfaces.”
The ad says“Demonstrated experience with high-speed digital layout: impedance-controlled routing, differential pairs, length matching, via optimization, and stack-up design for GHz-class interfaces.”
The ad says“Familiarity with IPC standards; IPC Certified Interconnect Designer (CID) or CID+ certification preferred but not required.”
The ad says“Expert-level proficiency in Altium Designer for schematic capture and PCB layout; comfort with rule-driven design, layer stack management, and library administration.”
The ad says“Expert-level proficiency in Altium Designer for schematic capture and PCB layout; comfort with rule-driven design, layer stack management, and library administration.”
The ad says“Demonstrated experience designing and laying out power electronics: DC/DC converters, power planes, bus bars/high-current traces, thermal management, and power protection schemes (e.g., fusing, current limiting).”
The ad says“Working knowledge of signal integrity (SI) and power integrity (PI) concepts and how layout decisions affect them; experience collaborating with SI/PI engineers or running basic simulation/analysis a plus.”
The ad says“Working knowledge of signal integrity (SI) and power integrity (PI) concepts and how layout decisions affect them; experience collaborating with SI/PI engineers or running basic simulation/analysis a plus.”

Apptronik is a human-centered robotics company developing AI-powered robots to support humanity in every facet of life. Our flagship humanoid robot, Apollo, is built to collaborate thoughtfully with people, starting with critical industries such as manufacturing and logistics, with future applications in healthcare, the home, and beyond.

We operate at the cutting edge of Applied AI, applying our expertise across the full robotics stack to solve some of society's most important problems. You will join a team dedicated to bringing Apollo to market at scale, tackling the complex challenges like safety, commercialization, and mass production to change the world for the better.

JOB SUMMARY

We're looking for a Senior ECAD Designer to own PCB schematic capture and layout in Altium Designer, with particular depth in power electronics and high-speed digital design. You will take boards from architecture and stack-up definition through layout, incorporating best practices such as design-for-manufacturability (DFM), signal integrity, power integrity, and EMC. In this role, you will partner closely with electrical, mechanical, and manufacturing teams to deliver reliable, production-ready designs on schedule.

ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES

PCB Design & Layout: Perform schematic capture and PCB layout for mixed-signal, power, and high-speed digital boards. Define stack-up, layer count, and material selection to meet electrical, thermal, and cost targets.
Power Design: Design and route power delivery networks, accounting for current-carrying capacity, copper weight, and thermal reliefs for layouts of DC/DC converters, power switching circuits, and bus/rail distribution for optimal power integrity.
High-Speed Design: Implement controlled-impedance routing, differential pair routing, length matching/tuning, and via strategy for high-speed interfaces (e.g., PCIe, DDR, USB, Ethernet, LVDS, SerDes).
DFM / DFA: Apply design-for-manufacturability and design-for-assembly best practices; partner with PCB fabricators and contract manufacturers (CMs) on design rule checks, panelization, tolerancing, and yield/cost tradeoffs.
EMC / EMI: Apply grounding, shielding, filtering, and layer-stack techniques to mitigate EMI/EMC risk, and support pre-compliance and regulatory testing (e.g., CE, FCC, UL) as needed.
Standards & Compliance: Design and document to relevant IPC standards (e.g., IPC-2221, IPC-6012, IPC-2152) and internal design rules; maintain and evolve design rule sets, layer stack templates, and library standards.
Documentation: Generate complete manufacturing outputs — Gerbers, drill files, BOMs, fabrication drawings, and assembly drawings — along with clear design documentation and constraint files. Support engineers with design releases in the product lifecycle management system.
Library Management: Create and maintain Altium schematic symbols, PCB footprints, and component library data in alignment with company library standards and part-lifecycle requirements.
Cross-Functional Collaboration: Work closely with electrical, mechanical, thermal, and manufacturing engineers to align layout with system requirements; participate in design reviews and provide layout feasibility input early in the design cycle. Drive discussions with ECAD software vendors on renewals, product selections, and software bugs with the oversight of the electrical engineering manager.
Mentorship: Act as a technical mentor to junior/mid-level designers on layout best practices, documentation standards, and use of Altium tools.

SKILLS AND REQUIREMENTS

Expert-level proficiency in Altium Designer for schematic capture and PCB layout; comfort with rule-driven design, layer stack management, and library administration.
Demonstrated experience designing and laying out power electronics: DC/DC converters, power planes, bus bars/high-current traces, thermal management, and power protection schemes (e.g., fusing, current limiting).
Demonstrated experience with high-speed digital layout: impedance-controlled routing, differential pairs, length matching, via optimization, and stack-up design for GHz-class interfaces.
Working knowledge of signal integrity (SI) and power integrity (PI) concepts and how layout decisions affect them; experience collaborating with SI/PI engineers or running basic simulation/analysis a plus.
Solid understanding of DFM/DFA principles and hands-on experience working directly with fabrication houses and contract manufacturers.
Practical knowledge of EMC/EMI mitigation techniques in layout (grounding, shielding, plane splits, filtering placement).
Familiarity with IPC standards; IPC Certified Interconnect Designer (CID) or CID+ certification preferred but not required.
Experience with flex, rigid-flex, or HDI/microvia design a plus.
Strong written and verbal communication skills; ability to produce clear design documentation and communicate tradeoffs to cross-functional stakeholders.
Ability to manage multiple concurrent design projects and mentor/provide work direction to other designers.
Ability to thrive in a fast-paced, high-growth environment where "perfect" is the enemy of "shipped," knowing exactly when a design is robust enough for the real world.

EDUCATION and/or EXPERIENCE

Bachelor’s degree in Electrical Engineering or equivalent experience.
At least 5 years of experience in PCB schematic capture and layout design.

PHYSICAL REQUIREMENTS

Prolonged periods of sitting at a desk and working on a computer
Must be able to lift 15 pounds at times
Vision to read printed materials and a computer screen
Hearing and speech to communicate

*This is a direct hire. Please, no outside Agency solicitations.

Apptronik provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.