Asks for

The ad says“• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.”
The ad says“• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)”
The ad says“• Proficiency in hardware debug tools, waveform viewers, and logic analyzers”
The ad says“• Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM”
The ad says“• Proficiency in hardware debug tools, waveform viewers, and logic analyzers”
The ad says“• Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM”
The ad says“• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)”
The ad says“• Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM”
The ad says“• Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development”
The ad says“• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)”
The ad says“• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)”
The ad says“• Set up and maintain Siemens Veloce emulation and prototyping platforms”
The ad says“• Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development”
The ad says“• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.”
The ad says“• Set up and maintain Siemens Veloce emulation and prototyping platforms”
The ad says“• Familiarity with UVM, simulation, and testbench environments. SystemVerilog and UVM-based verification experience a plus”
The ad says“• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.”
The ad says“• BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience.”
The ad says“• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.”
The ad says“• Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development”
The ad says“• Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM”
The ad says“• Familiarity with UVM, simulation, and testbench environments. SystemVerilog and UVM-based verification experience a plus”
The ad says“• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)”
The ad says“• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.”
The ad says“• Proficiency in hardware debug tools, waveform viewers, and logic analyzers”
The ad says“• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)”

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Senior Emulation Engineer

Location: India - Remote

Job Description:

At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built

for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you

will play a critical role in validating complex AI accelerator architectures on emulation

platforms before tape-out. This position is ideal for someone passionate about bridging the

gap between hardware and software in fast-paced, deep tech environments.

Responsibilities:

• Set up and maintain Siemens Veloce emulation and prototyping platforms

• Adapt SoC designs for Emulation and Prototyping

• Develop and debug emulation testbenches and system-level environments

• Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation.

• Collaborate with design and verification teams to isolate design issues and accelerate debug.

• Optimize performance of the emulation workloads and reduce turnaround time.

• Work with firmware/software teams to enable use of emulators for OS and driver testing.

Required Background:

• BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience.

• Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium)

• Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM

• Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.

• Proficiency in hardware debug tools, waveform viewers, and logic analyzers

• Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development

• Familiarity with UVM, simulation, and testbench environments. SystemVerilog and UVM-based verification experience a plus

• Hand-on software development experience with C/C++ is a plus

Asks for

Values