Asks for

The ad says“Design in Altium; produce layout-ready packages with full design rule documentation for contract manufacturing”
The ad says“Develop and execute high-speed board bring-up: BERT testing, TDR characterization, eye mask compliance, and EMC pre-compliance”
The ad says“Own signal integrity from component selection and schematic capture through layout and post-route simulation: impedance control, differential pair routing, crosstalk analysis, and eye diagram verification.”
The ad says“Own signal integrity from component selection and schematic capture through layout and post-route simulation: impedance control, differential pair routing, crosstalk analysis, and eye diagram verification.”
The ad says“Select and implement best design practices that minimize the down-stream risk of test failures from EMI/EMC. Familiar with industry standards such as STD-461, DO-160, and MIL-STD-461.”
The ad says“Develop and execute high-speed board bring-up: BERT testing, TDR characterization, eye mask compliance, and EMC pre-compliance”
The ad says“Own signal integrity from component selection and schematic capture through layout and post-route simulation: impedance control, differential pair routing, crosstalk analysis, and eye diagram verification.”
The ad says“Develop and execute high-speed board bring-up: BERT testing, TDR characterization, eye mask compliance, and EMC pre-compliance”
The ad says“This is a hands-on design role. You will own high-speed digital PCB design, signal integrity, and FPGA development across a range of programs - from space avionics and optical communication systems to power electronics and embedded computing platforms. No two programs are identical, and you will bring the same first-principles rigor to each one.”
The ad says“Experience with high-speed test equipment and debug tools: BERT, VNA, TDR, high-bandwidth oscilloscopes (20 GHz+), and logic analyzers.”
The ad says“This is a hands-on design role. You will own high-speed digital PCB design, signal integrity, and FPGA development across a range of programs - from space avionics and optical communication systems to power electronics and embedded computing platforms. No two programs are identical, and you will bring the same first-principles rigor to each one.”
The ad says“Own signal integrity from component selection and schematic capture through layout and post-route simulation: impedance control, differential pair routing, crosstalk analysis, and eye diagram verification.”
The ad says“Experience with high-speed test equipment and debug tools: BERT, VNA, TDR, high-bandwidth oscilloscopes (20 GHz+), and logic analyzers.”
The ad says“Select and implement best design practices that minimize the down-stream risk of test failures from EMI/EMC. Familiar with industry standards such as STD-461, DO-160, and MIL-STD-461.”
The ad says“Work with power electronics engineers to inform and design power delivery networks for high-performance ASICs, FPGAs, and multi-channel memory; close power budgets from system architecture through regulator selection and decoupling strategy”
The ad says“Incorporate environmental requirements across programs: radiation tolerance, thermal cycling, vibration, shock, and vacuum outgassing where applicable”
The ad says“Incorporate environmental requirements across programs: radiation tolerance, thermal cycling, vibration, shock, and vacuum outgassing where applicable”
The ad says“This is a hands-on design role. You will own high-speed digital PCB design, signal integrity, and FPGA development across a range of programs - from space avionics and optical communication systems to power electronics and embedded computing platforms. No two programs are identical, and you will bring the same first-principles rigor to each one.”
The ad says“Select and implement best design practices that minimize the down-stream risk of test failures from EMI/EMC. Familiar with industry standards such as STD-461, DO-160, and MIL-STD-461.”
The ad says“Develop and execute high-speed board bring-up: BERT testing, TDR characterization, eye mask compliance, and EMC pre-compliance”
The ad says“Incorporate environmental requirements across programs: radiation tolerance, thermal cycling, vibration, shock, and vacuum outgassing where applicable”
The ad says“Incorporate environmental requirements across programs: radiation tolerance, thermal cycling, vibration, shock, and vacuum outgassing where applicable”
The ad says“Incorporate environmental requirements across programs: radiation tolerance, thermal cycling, vibration, shock, and vacuum outgassing where applicable”
The ad says“Experience with high-speed test equipment and debug tools: BERT, VNA, TDR, high-bandwidth oscilloscopes (20 GHz+), and logic analyzers.”

Role Overview:

We are looking for a High Speed Digital Electrical Engineer to work across client programs that demand hardware performing at the edge of what is commercially possible.

This is a hands-on design role. You will own high-speed digital PCB design, signal integrity, and FPGA development across a range of programs - from space avionics and optical communication systems to power electronics and embedded computing platforms. No two programs are identical, and you will bring the same first-principles rigor to each one.

You will work alongside engineers who have shipped flight hardware and know what it takes to close a design in a real program environment. You will have direct client exposure, ownership over your technical deliverables, and access to programs that rarely show up at larger firms.

As SOE grows our incubation model, high-speed digital engineering sits at the center of the most technically demanding programs we take on. This role is a direct line into that work.

Key Responsibilities:

High Speed Digital Design:

Support high speed electrical architecture from concept generation through investigation including key trades, requirement definition, investigations and component selection.
Own signal integrity from component selection and schematic capture through layout and post-route simulation: impedance control, differential pair routing, crosstalk analysis, and eye diagram verification.
Work with power electronics engineers to inform and design power delivery networks for high-performance ASICs, FPGAs, and multi-channel memory; close power budgets from system architecture through regulator selection and decoupling strategy
Develop and execute high-speed board bring-up: BERT testing, TDR characterization, eye mask compliance, and EMC pre-compliance
Design in Altium; produce layout-ready packages with full design rule documentation for contract manufacturing

Space Qualification & EMI/EMC:

Incorporate environmental requirements across programs: radiation tolerance, thermal cycling, vibration, shock, and vacuum outgassing where applicable
Select and qualify components for space-grade or radiation-tolerant operation; manage parts lists and evaluate COTS mitigation strategies
Select and implement best design practices that minimize the down-stream risk of test failures from EMI/EMC. Familiar with industry standards such as STD-461, DO-160, and MIL-STD-461.
Author and maintain design specifications, interface control documents, and test procedures at the level demanding programs require

Client & Team Collaboration:

Work directly with clients to translate system requirements into board-level hardware specifications
Contribute to technical reviews (PDR, CDR) as both a presenter and reviewer across programs
Support junior engineers through design reviews and hands-on mentorship
Contribute to SOE's internal body of knowledge: reusable design patterns, documentation standards, and lessons learned

Minimum Qualifications:

Bachelor's Degree (Electrical Engineering, Computer Science, Physics, Math, or related field)
5+ years of applied experience with a demonstrated passion for engineering and technology development
Experience with high-speed test equipment and debug tools: BERT, VNA, TDR, high-bandwidth oscilloscopes (20 GHz+), and logic analyzers.
Excellent written and verbal technical communication skills; ability to explain technical concepts and their implications to non-technical audiences
A systems-thinking approach, with the ability to connect engineering execution to business strategy.
A proven track record of leading technical initiatives, mentoring engineers, and driving process improvements.
A bias for action, thriving in a fast-paced consulting environment where priorities can shift quickly.
Willingness to be deeply involved in both high-level strategy and hands-on technical execution.

Preferred Qualifications:

10+ years of relevant experience
Experience designing electronics for space-qualified or radiation-tolerant applications, including component derating, single-event effects (SEE) analysis, or environmental test campaigns (thermal vacuum, vibration, shock)
Familiarity with 400G/800G Ethernet architectures, PAM4 signaling, or co-packaged optics interfaces
Experience with power integrity analysis tools and multi-phase VRM design for high-current, fast-transient loads
Background in optical communication systems or the electrical interface between high-speed digital hardware and analog RF or opto-electronic signal chains
EMI/EMC test experience to MIL-STD-461 or DO-160
Experience with business development, sales engineering, or technical sales to support the CEO in client engagements.
Prior work in an engineering consulting or services-based firm, understanding the nuances of client-driven project work.
Understanding of operations, finance, or project management, helping streamline engineering execution at a business level.
A history of patents, publications, or open-source contributions, demonstrating thought leadership in the field.

Additional Requirements:

Applicant must be willing to work 40 hours a week on-site in El Segundo, California, USA
Applicant must be eligible to work on ITAR projects
Job Type: Full-time (Salary)
To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Unfortunately, we are unable to provide sponsorship at this time.

Compensation and Benefits:

Salary range dependent on leveling
- Senior Engineer: $155,000 - $200,000
- Staff Engineer: $195,000 - $235,000
- Principal Engineer: $235,000 - $270,000
Equity (via ISOs) in Second Order Effects, Inc.
Equity (via PIUs) in our incubated companies (through our holding company, Second Order Holdings, LLC)
100% employer-paid health insurance (Medical, Dental, Vision) for employees + 50% dependent coverage
Flexible paid time off policy + 11 paid holidays + 12 paid sick days
401(k) retirement account and employer matching (Safe Harbor 4%)
Up to 22 weeks of paid parental leave dedicated to new child bonding
Relocation assistance available if 50+ miles away from the office
Electric Vehicle (EV) charging ports
Daily catered lunches, snacks, and accessible kitchen

Asks for

Values