Asks for

The ad says“Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development”
The ad says“Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation”
The ad says“Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation”
The ad says“Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs”
The ad says“Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation”
The ad says“Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation”
The ad says“Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development”
The ad says“Strong programming and scripting skills in Perl, Python or Tcl desired”
The ad says“Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs”
The ad says“Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs”
The ad says“Strong programming and scripting skills in Perl, Python or Tcl desired”
The ad says“Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs”
The ad says“Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation”
The ad says“Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development”
The ad says“Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs”
The ad says“Strong programming and scripting skills in Perl, Python or Tcl desired”
The ad says“Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development”
The ad says“Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools”
The ad says“Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools”

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
In addition, you will help develop and deploy DFT methodologies for our next generation products.
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

What we need to see:

BSEE (or equivalent experience) with 5+, MSEE with 3+ years of experience or PhD in DFT or related domains
Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Strong programming and scripting skills in Perl, Python or Tcl desired
Extraordinary written and oral communication skills with the curiosity to work on rare challenges

Our technology has no boundaries! NVIDIA is building the world’s most groundbreaking and state of the art compute platforms for the world to use. It’s because of our work that scientists, researchers and engineers can advance their ideas. At its core, our visual computing technology not only enables an outstanding computing experience, but it is also energy efficient! We pioneered a supercharged form of computing loved by the most demanding computer users in the world - scientists, designers, artists, and gamers.

NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you!

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 8, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.