Senior ASIC layout design engineer_BST

Asks for

• analog layout designThe ad says“As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor. You will work with international design team to ensure the layout delivery on time and in quality, then execute whole tape-out flow together with wafer foundry. Work with digital backend engineer to generate DFE file for P&R and integrated digital layout into whole chip. You will also work with CAD engineers to continuously improve our PDKs and design environment.”
• analog/mix-signal integrated circuit layoutThe ad says“8 or above years’ experience in analog/mix-signal integrated circuit layout for ADCs, DACs, PLLs, LDOs, Charge pump, bandgap design”
• AssuraThe ad says“Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools, and understand the runset （Calibre, PVS, Assura, etc.… ）”
• C shellThe ad says“Be able to use at least one programming language to develop scripts to improve the layout effeciency, including C shel, SKILL, TCL, Python”
• Cadence VirtuosoThe ad says“Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools, and understand the runset （Calibre, PVS, Assura, etc.… ）”
• CalibreThe ad says“Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools, and understand the runset （Calibre, PVS, Assura, etc.… ）”
• EM analysisThe ad says“Be able to analysis EM and IR drop”
• floorplan creationThe ad says“Able to independently create floorplan on chip level by balance the area, performance, schedule”
• IR drop analysisThe ad says“Be able to analysis EM and IR drop”
• physical verificationThe ad says“As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor. You will work with international design team to ensure the layout delivery on time and in quality, then execute whole tape-out flow together with wafer foundry. Work with digital backend engineer to generate DFE file for P&R and integrated digital layout into whole chip. You will also work with CAD engineers to continuously improve our PDKs and design environment.”
• PVSThe ad says“Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools, and understand the runset （Calibre, PVS, Assura, etc.… ）”
• PythonThe ad says“Be able to use at least one programming language to develop scripts to improve the layout effeciency, including C shel, SKILL, TCL, Python”
• SKILLThe ad says“Be able to use at least one programming language to develop scripts to improve the layout effeciency, including C shel, SKILL, TCL, Python”
• TCLThe ad says“Be able to use at least one programming language to develop scripts to improve the layout effeciency, including C shel, SKILL, TCL, Python”