Asks for

The ad says“Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices (e.g. Finfet transistors).”
The ad says“Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem …) and familiarity with layout design flows for advanced technology nodes.”
The ad says“High level of proficiency in interpreting DRC, PERC, ANT, ERC and LVS”
The ad says“Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem …) and familiarity with layout design flows for advanced technology nodes.”
The ad says“Solid understanding of RC delay, electromigration, and coupling effects.”
The ad says“Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices (e.g. Finfet transistors).”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE”
The ad says“High level of proficiency in interpreting DRC, PERC, ANT, ERC and LVS”
The ad says“Solid understanding of RC delay, electromigration, and coupling effects.”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“High level of proficiency in interpreting DRC, PERC, ANT, ERC and LVS”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices (e.g. Finfet transistors).”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“Familiarity with semiconductor manufacturing processes and foundry technologies.”
The ad says“Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE”
The ad says“High level of proficiency in interpreting DRC, PERC, ANT, ERC and LVS”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE”
The ad says“High level of proficiency in interpreting DRC, PERC, ANT, ERC and LVS”
The ad says“Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE”
The ad says“Solid understanding of RC delay, electromigration, and coupling effects.”
The ad says“Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.”
The ad says“Familiarity with semiconductor manufacturing processes and foundry technologies.”
The ad says“Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem …) and familiarity with layout design flows for advanced technology nodes.”
The ad says“Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE”

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

What will you do at Ciena as a Analog Layout Engineer?

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track-record of success over 30-years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions.

To further strengthen our team, we are looking for a hardworking analog layout engineer who will be working on advanced high-speed analog design circuits in the latest deep-submicron CMOS and/or BiCMOS technologies. Your role as an analog layout engineer will be to drive and implement best-in-class high-speed analog layouts that extract the highest performance from the world’s most advanced CMOS and BiCMOS technologies. These analog macros include electrical interface-facing DAC and ADC based SERDES solutions for 112G and 224G, optical-line-facing high-speed DAC and ADC circuits interfacing with optical modulators and detectors, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions, etc.

Responsibilities:

Carry out layout feasibility studies on various circuit designs in collaboration with senior analog designers. The goal will be to find the best possible solution considering various trade-offs and discussions with team members.

Create layouts of assigned analog blocks by adhering to the steps of floor planning, placement and routing.
Conduct thorough verification checks such as DRC, ANT, LVS, PERC, EM, IR to ensure the final layout possesses the highest level of quality.
Investigate new features within the layout tools and processes used for creating layouts with the aim of enhancing productivity.
Provide regular status updates, participate in team meetings and share experiences with the rest of the group.

What technical experience and personal skills are required for this role?

Bachelor's degree in Electrical Engineering or related field, with 1-5 years of relevant industry experience.
Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices (e.g. Finfet transistors).
Highly motivated with strong team player skills, exhibits a positive can-do attitude and ability to seamlessly integrate into an existing team culture.
Strong communication and interpersonal skills to collaborate with cross-functional teams.
Experience in custom layout design of Analog/Mixed Signal designs (e.g. ADC, DAC, PLL, SERDES …)
Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem …) and familiarity with layout design flows for advanced technology nodes.
Strong analytical and problem-solving skills to identify and address layout-related issues efficiently.
Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.
Meticulous attention to details, ensuring the highest level of accuracy and quality in all layout designs.
Familiarity with semiconductor manufacturing processes and foundry technologies.
Ability to thrive in a fast-paced, dynamic work environment and adapt quickly to changing project requirements.
Solid understanding of RC delay, electromigration, and coupling effects.
Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE
High level of proficiency in interpreting DRC, PERC, ANT, ERC and LVS
Ability to identify failure-prone circuit and layout structures and proactively work with circuit designers to resolve problems.
Scripting skills in PERL or SKILL are a plus, but not required.

The above statements are intended to describe the work being performed by people assigned to this job. They are not intended to be an exhaustive list of all responsibilities, duties and skills required. The duties and responsibilities of this position are subject to change and other duties may be assigned or removed at any time. You will have an opportunity to better understand the role through the interview experience.

Pay Range: The annual salary range is $114,000 - $182,000 CAD

Vacancy Status: Future Opportunity

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Asks for

Values