Asks for

The ad says“You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.”
The ad says“· Formal verification (Synopsys Formality / Cadence Conformal)”
The ad says“· Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler”
The ad says“· Familiarity with DFT (design for test) and scan methodology”
The ad says“· Formal verification (Synopsys Formality / Cadence Conformal)”
The ad says“· Version control (svn, git, etc)”
The ad says“· Understanding of liberty LIB models for timing”
The ad says“· TCL/Perl scripting”
The ad says“· Power analysis of RTL and gate level netlists”
The ad says“· Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries”
The ad says“· Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.”
The ad says“· Familiarity with DFT (design for test) and scan methodology”
The ad says“· Spyglass Lint”
The ad says“· Version control (svn, git, etc)”
The ad says“· Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler”
The ad says“· Formal verification (Synopsys Formality / Cadence Conformal)”
The ad says“· TCL/Perl scripting”
The ad says“· Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries”
The ad says“You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.”

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Job Description:

You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.

· Ability to work independently as well as part of a large team spanning multiple geographies.

· Education: BS/MS in Electrical or Computer Engineering or equivalent

· Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience

· Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.

· Requires proficiency with the following design tools / flows:

· TCL/Perl scripting

· Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler

· Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries

· Understanding of liberty LIB models for timing

· Formal verification (Synopsys Formality / Cadence Conformal)

· Spyglass Lint

· Power analysis of RTL and gate level netlists

· Familiarity with DFT (design for test) and scan methodology

· Version control (svn, git, etc)

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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