Asks for

The ad says“3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.”
The ad says“2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.”
The ad says“2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.”
The ad says“2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.”
The ad says“3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.”
The ad says“2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.”
The ad says“2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.”
The ad says“2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.”
The ad says“3+ years of experience with physical design implementation of custom IP or SoC designs from RTL through GDSII.”
The ad says“3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.”
The ad says“3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.”
The ad says“2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.”
The ad says“2+ years of experience performing static timing analysis (STA) and supporting timing closure on semiconductor designs.”
The ad says“3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.”

Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

We are seeking a Physical Design Engineer to join our Silicon Design Automation & Implementation organization. In this role, you will contribute to the implementation of custom IP and SoC designs from RTL through GDSII, supporting timing closure, power optimization, physical verification, and design signoff for leading-edge semiconductor products. You will work closely with architecture, RTL, DFT, synthesis, verification, and methodology teams to help deliver high-quality silicon for next-generation FPGA technologies.

Key Responsibilities

Perform block-level physical design implementation of custom IP and SoC designs from RTL through GDSII, supporting the delivery of manufacturing-ready design databases.
Execute and support stages of the physical design flow, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing analysis, and physical optimization.
Perform static timing analysis (STA) and help resolve setup, hold, signal integrity, and other timing violations to achieve design closure.
Support the development and optimization of clock distribution networks, power distribution networks, and multiple power domain implementations to meet performance, power, and reliability targets.
Participate in physical verification and signoff activities, including formal equivalence checking (LEC), static timing analysis, power integrity, IR drop, electromigration (EM), layout verification, electrical rule checking (ERC), design rule checking (DRC), layout versus schematic (LVS), and structural verification.
Analyze physical design results, identify root causes of implementation issues, and work with senior engineers and cross-functional teams to implement corrective actions.
Optimize physical implementations to improve product-level metrics including performance, power consumption, frequency, area (PPA), manufacturability, and reliability.
Collaborate closely with RTL, Logic Design, DFT, CAD, Architecture, Verification, and Product Engineering teams throughout the design cycle.
Support Design-for-Test (DFT) integration and implementation throughout physical design and signoff.
Support physical design convergence across multiple design iterations while balancing timing, power, congestion, and area tradeoffs.
Contribute to the development, enhancement, and automation of physical design methodologies, flows, and infrastructure.
Apply physical implementation best practices and contribute to continuous improvements in design quality and execution.

What You'll Bring

Strong understanding of semiconductor physical implementation methodologies and design flows.
Strong analytical and debugging skills for solving timing, congestion, and physical implementation challenges.
Ability to analyze power, performance, and area tradeoffs across SoC and custom IP designs.
Strong communication skills with the ability to collaborate effectively across multidisciplinary engineering teams.
Ability to work effectively in a fast-paced, collaborative semiconductor development environment.
Passion for building high-quality silicon and continuously improving engineering methodologies.

Why Join Altera?

At Altera, you'll help shape the future of programmable computing while working alongside some of the industry's most accomplished semiconductor engineers. We offer challenging technical problems, opportunities to influence next-generation FPGA products, competitive compensation, comprehensive benefits, and long-term wealth-building opportunities through our equity programs. If you're passionate about delivering world-class silicon and advancing physical design methodologies, we'd love to hear from you.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$118,900 - $169,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline and 3+ years of experience in semiconductor Physical Design.
3+ years of experience with physical design implementation of custom IP or SoC designs from RTL through GDSII.
3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.
2+ years of experience performing static timing analysis (STA) and supporting timing closure on semiconductor designs.
2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.

Preferred Qualifications

Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline.
Experience with advanced technology nodes (7nm, 5nm, 3nm, or smaller).
Experience implementing high-performance CPU, FPGA, AI accelerator, networking, or SoC designs.
Experience with Tcl, Python, Perl, or Shell scripting for flow automation.
Knowledge of static timing analysis and low-power implementation methodologies, including UPF/CPF.
Experience with Synopsys, Cadence, or Siemens EDA physical design and analysis tools.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.