Asks for

The ad says“Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).”
The ad says“Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).”
The ad says“Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).”
The ad says“Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).”
The ad says“Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).”
The ad says“Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).”
The ad says“Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).”
The ad says“Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).”
The ad says“Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).”
The ad says“A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes.”
The ad says“Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).”
The ad says“Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).”
The ad says“Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).”
The ad says“Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).”
The ad says“Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).”
The ad says“Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).”
The ad says“Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).”
The ad says“Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).”
The ad says“Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).”

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline.

This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes.
Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets.
Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room.

What We Need

BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout.
Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).
Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).
Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).

What You Will Learn

How RISC-V CPU and AI accelerator IP is hardened and delivered to external licensees on the most advanced process nodes.
Multi-variant IP delivery: porting the same block across nodes, foundries, and PPA targets.
Direct impact on IP deal timelines, since your PPA and schedule data feeds our customer commitments.
Front-to-back co-design with architecture, RTL, and chiplet integration teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.