Asks for

The ad says“Familiarity with back-drilling, via-in-pad, and other advanced fabrication techniques, plus DFM/DFT requirements (test point coverage, copper balance, solder mask, assembly constraints)”
The ad says“Experience with fine-pitch BGA placement/routing for AI ASICs, GPUs, or high-density packages, and hands-on work with high-speed interfaces (PCIe Gen5/6, CXL, DDR5, 112G/224G SerDes)”
The ad says“Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization”
The ad says“Familiarity with back-drilling, via-in-pad, and other advanced fabrication techniques, plus DFM/DFT requirements (test point coverage, copper balance, solder mask, assembly constraints)”
The ad says“Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization”
The ad says“Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization”
The ad says“Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization”
The ad says“Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization”
The ad says“7+ years of PCB layout experience, including complex multi-layer boards (20+ layers) for server, AI compute, networking, or similar high-performance hardware”
The ad says“Strong understanding of PDN design (VRM placement, decoupling strategy, power planes, current return paths) and stack-up design (layer count, impedance control, material selection, e.g. Megtron 6/8/9, TU-953Q)”
The ad says“Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization”
The ad says“Ability to interpret SI/PI simulation results and incorporate feedback into layout”
The ad says“Strong understanding of PDN design (VRM placement, decoupling strategy, power planes, current return paths) and stack-up design (layer count, impedance control, material selection, e.g. Megtron 6/8/9, TU-953Q)”
The ad says“Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization”
The ad says“Familiarity with back-drilling, via-in-pad, and other advanced fabrication techniques, plus DFM/DFT requirements (test point coverage, copper balance, solder mask, assembly constraints)”

What MatX Is Building

MatX is building next-generation AI compute infrastructure for large-scale LLM training and inference. We are looking for an experienced PCB Layout Engineer to design and deliver high-speed, high-power, high-density printed circuit boards for our AI chip, compute tray, and rack-scale platform. This is a hands-on role where layout quality directly impacts signal integrity, power integrity, and system performance.

What You'll Do Here

Own PCB layout from floorplanning through final Gerber release for complex, high-layer-count boards (AI accelerator boards, compute trays, backplanes)
Design high-speed differential pair and controlled impedance routing for PCIe Gen5/6, CXL, and Ethernet 112G/224G interfaces, including length matching and timing constraints per SI/PI guidelines
Plan stack-ups (layer assignment, impedance control, via structure, laminate selection) and place/route complex BGA packages, including AI ASICs
Design power delivery networks (PDN) — VRM placement, decoupling capacitors, and power planes to meet PI requirements, partnering with SI/PI engineers on simulation and pre/post-layout analysis
Ensure DFM/DFT/DFA compliance (test points, via-in-pad, back-drill, assembly constraints) and coordinate with mechanical engineers on board outline, keep-outs, and chassis constraints
Lead design, layout, and DFM reviews with JDM/ODM partners, and manage release packages (Gerbers, fabrication notes, stackup docs, footprint libraries)
Support bring-up, debug, and signal probing to resolve layout-related issues

Who You Are

7+ years of PCB layout experience, including complex multi-layer boards (20+ layers) for server, AI compute, networking, or similar high-performance hardware
Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization
Experience with fine-pitch BGA placement/routing for AI ASICs, GPUs, or high-density packages, and hands-on work with high-speed interfaces (PCIe Gen5/6, CXL, DDR5, 112G/224G SerDes)
Strong understanding of PDN design (VRM placement, decoupling strategy, power planes, current return paths) and stack-up design (layer count, impedance control, material selection, e.g. Megtron 6/8/9, TU-953Q)
Familiarity with back-drilling, via-in-pad, and other advanced fabrication techniques, plus DFM/DFT requirements (test point coverage, copper balance, solder mask, assembly constraints)
Ability to interpret SI/PI simulation results and incorporate feedback into layout
Experience releasing fabrication packages (Gerbers, drill files, stackup specs) and working directly with PCB fabricators and JDM/ODM partners on high-speed, high-layer-count boards

Bonus Points

Experience with 5nm or 3nm and below AI ASIC board layout, ultra-fine pitch BGA, high-density routing
Experience with 224G PAM4 high-speed interface routing and material selection
Knowledge of fiber weave effect mitigation — routing at 45°, spread glass laminates
Familiarity with OCP Open Rack board form factors and mechanical constraints
Experience with power integrity simulation tools (Ansys SIwave, Cadence Sigrity)
Background in EMI/EMC design, stitching vias, ground guard traces, and shielding techniques

Compensation

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job-related skills, and relevant education and training. Career length is only a guideline for compensation.

Early Career - $160,000 - $275,000 + equity
Mid Career - $175,000 - $400,000 + equity
Senior Career - $250,000 - $600,000 + equity

What We Offer

Time off: 4 weeks PTO (accrued) + 12 company Holidays + up to 3 weeks remote work
Health: Company-subsidized Medical (Kaiser or Anthem) for employees & dependents, Guardian Dental and Vision insurances for employee & dependents, and life insurance (employee only), plus HSA and FSA offerings via Lively.
Financial Security: Choose from Roth or pre-tax 401K (or both) with a 5% company contribution (even if you don't contribute), 100% company-paid life insurance (up to $300K), long-term disability and travel insurance.
Professional Development: $1500 per year Professional Development Budget
Team Meals: MatX provides onsite team lunch & dinner Monday - Friday, with your choice of ordering via WeBox, Specialty’s or via our reimbursement system
Commute on Us: We pay 100% for your daily commute. Commute via our company rideshare account, reimburse public transportation, or get a Fasttrak card (or all three)
MatX E[x]tras: $50/mo to use on the perk you value most
Cell & Internet Reimbursement: $35/mo for cellular and $40/mo for wifi
Remote Home Setup: Use our Amazon business account for up to $1000 in office setup purchases.
Mental Wellbeing: 100% paid mental health benefit via SpringHealth and Guardian EAP.
Support to Parents: Up to 12 weeks paid parental leave regardless of path to parenthood, 10 weeks pregnancy disability leave, flexible return-to-work hours, and a $6K Family Fund to cover fertility, surrogacy, adoption, menopausal health, preservation, family counseling and more.

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.
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This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicant's capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
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MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.