Asks for

The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”
The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”
The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”
The ad says“As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.”
The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”
The ad says“As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.”
The ad says“As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.”
The ad says“As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.”
The ad says“• Lead a team responsible for design implementation and verification through post-silicon validation.”
The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”
The ad says“As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.”
The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”
The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”
The ad says“• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).”

Values

The ad says“As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.”
The ad says“As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.”
The ad says“• Experience with pre-silicon enablement via emulation or FPGA prototyping.”
The ad says“• Experience with pre-silicon enablement via emulation or FPGA prototyping.”
The ad says“• Experience with low-power (UPF) methods and security features such as Root of Trust and secure boot.”
The ad says“• Partner with physical/custom design engineers, often first prototyping blocks through place-and-route prior to hand-off, and co-design critical custom circuits such as memories to achieve the best KPIs.”
The ad says“• Experience with low-power (UPF) methods and security features such as Root of Trust and secure boot.”
The ad says“• Experience with low-power (UPF) methods and security features such as Root of Trust and secure boot.”

Job Details:

Job Description:

The Opportunity For nearly a decade, Intel's Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach. Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators. If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads. Position Overview As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential. Responsibilities • Engage with architects and AI researchers to identify hardware innovations and optimizations, and translate them into implementable microarchitectures. • Lead a team responsible for design implementation and verification through post-silicon validation. • Partner with physical/custom design engineers, often first prototyping blocks through place-and-route prior to hand-off, and co-design critical custom circuits such as memories to achieve the best KPIs. • Evaluate, select, and integrate internal and external IP, including I/O interfaces. • Work with software and systems teams to enable development long before tape-out and ensure smooth post-silicon bring-up. • Mentor engineers and strengthen design and verification practices as the program scales.

Qualifications:

Minimum qualifications
• MS in Electrical/Computer Engineering, Computer Science, or a related field.
• 10+ years of hands-on design experience in processors, accelerators, SoCs, or custom ASICs.
• 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).
• 3+ years leading silicon design and/or verification teams.

Preferred qualifications
• PhD with a research background in hardware acceleration, especially AI.
• Experience with advanced packaging and heterogeneous integration technologies (e.g., chiplets, UCIe, 2.5D/3D).
• Experience with asynchronous design methods and custom memory/circuit co-design.
• Experience with pre-silicon enablement via emulation or FPGA prototyping.
• Experience with low-power (UPF) methods and security features such as Root of Trust and secure boot.

• History of technical ownership on multiple product tape-outs.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.