Asks for

The ad says“- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.”
The ad says“- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).”
The ad says“- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).”
The ad says“- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).”
The ad says“- Proficiency in floor-planning, hierarchy layout, and chip integration.”
The ad says“- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.”
The ad says“- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.”
The ad says“- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.”
The ad says“- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.”
The ad says“- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.”
The ad says“- Proficiency in floor-planning, hierarchy layout, and chip integration.”
The ad says“- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).”
The ad says“- Proficiency in floor-planning, hierarchy layout, and chip integration.”
The ad says“- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).”
The ad says“- Minimum 3 years of experience with strong layout knowledge”
The ad says“- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.”
The ad says“- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines”
The ad says“- Good knowledge of memory layout topology; experience with memory compilers is a plus.”
The ad says“- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.”
The ad says“- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines”
The ad says“- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).”
The ad says“- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.”
The ad says“- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).”
The ad says“- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.”

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Job Description:

Job Requirements:
- Minimum 3 years of experience with strong layout knowledge
- Bachelor's degree required.
- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).
- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).
- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description:
- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
- Manage scheduling, timelines, and layout floor-planning.

- Responsible for start to end deliverables with quality within the planned schedule.
- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.

Skill Set (Memory):
- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
- Proficiency in floor-planning, hierarchy layout, and chip integration.
- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines
- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.
- Ability to lead, train junior engineers, and manage projects effectively.
- Good knowledge of memory layout topology; experience with memory compilers is a plus.
- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
- Self-reliant with the ability to work both independently and collaboratively.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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Asks for

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Job Description: