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Memory Design Engineer at Allegro MicroSystems Philippines, Inc. (Philippines) · Katori

Asks for

The ad says“EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.”
The ad says“A qualified candidate requires a BSEE with a minimum of 2 years of experience in the industry. Experience must include memory and mix-signal transistor-level design, circuit verification, and silicon testing.”
The ad says“Digital components (logic, memory, EEPROM, TAP controllers, JTAG, FPGA, serial data communication protocols, microprocessors and microcontrollers).”
The ad says“EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.”
The ad says“SW Experience includes the basic understanding of HDL languages (Verilog, VerilogA, and VerilogAMS). Skill, C, and SystemVerilog are a plus.”
The ad says“EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.”
The ad says“Experience with layout parasitic/leakage design trade-offs.”
The ad says“A qualified candidate requires a BSEE with a minimum of 2 years of experience in the industry. Experience must include memory and mix-signal transistor-level design, circuit verification, and silicon testing.”
The ad says“Ability to work with design teams on memory debug and diagnostics.”
The ad says“Ability to develop Memory test/validation plans.”
The ad says“Ability to characterize Memory/Standard Cells in standard liberty format.”
The ad says“EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.”
The ad says“EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.”
The ad says“The Senior IP Engineer will report to the Director of Design Enablement and will play a critical role in supporting the Design Enablement team. This role will perform semiconductor device layouts in EDA software environment for semiconductor technology development and device modeling. In addition, this role will support the release of Foundry mask manufacturing requirements for a global design community. Candidate will design and verify standard IP memories that include Single-Port SRAM, Register File, ROM, One-Time-Programmable, EEPROM, and FLASH. This work directly impacts the development of our BCD technology and the success of our global design community.”
The ad says“A qualified candidate requires a BSEE with a minimum of 2 years of experience in the industry. Experience must include memory and mix-signal transistor-level design, circuit verification, and silicon testing.”
The ad says“Solid understanding of modeling challenges for sub-micron technologies.”
The ad says“SW Experience includes the basic understanding of HDL languages (Verilog, VerilogA, and VerilogAMS). Skill, C, and SystemVerilog are a plus.”
The ad says“SW Experience includes the basic understanding of HDL languages (Verilog, VerilogA, and VerilogAMS). Skill, C, and SystemVerilog are a plus.”
The ad says“SW Experience includes the basic understanding of HDL languages (Verilog, VerilogA, and VerilogAMS). Skill, C, and SystemVerilog are a plus.”
The ad says“EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.”
The ad says“EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.”

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.

About the Department

The Technology Development group is an integral organization of Allegro that includes Device Development, Foundry Operations, Modeling, ESD/EMC, and Design Enablement teams. The group facilitates all semiconductor devices and design automation research and development programs from concept through maturity. We ensure that the technology roadmap is aligned with the product roadmap and work across organizations. We manage partnerships with external foundries and suppliers to deliver cutting-edge semiconductor devices and design automation tools to support the product roadmap.

The Opportunity

The Senior IP Engineer will report to the Director of Design Enablement and will play a critical role in supporting the Design Enablement team. This role will perform semiconductor device layouts in EDA software environment for semiconductor technology development and device modeling. In addition, this role will support the release of Foundry mask manufacturing requirements for a global design community. Candidate will design and verify standard IP memories that include Single-Port SRAM, Register File, ROM, One-Time-Programmable, EEPROM, and FLASH. This work directly impacts the development of our BCD technology and the success of our global design community.

What You Will Do

Design NVM, VM, driver circuit, and digital IP.
IP in silicon test and validation.
Coordinate design requirements, macro floor planning, and layout design.
Characterization and standardization of memory/digital IP for global design use within a custom PDK environment.
Documentation development and publishing of IP specifications and application use cases.

What You Will Need

A qualified candidate requires a BSEE with a minimum of 2 years of experience in the industry. Experience must include memory and mix-signal transistor-level design, circuit verification, and silicon testing.

Applications knowledge of the following is required:

Digital components (logic, memory, EEPROM, TAP controllers, JTAG, FPGA, serial data communication protocols, microprocessors and microcontrollers).
Ability to develop Memory test/validation plans.
Ability to characterize Memory/Standard Cells in standard liberty format.
Ability to work with design teams on memory debug and diagnostics.
EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.
SW Experience includes the basic understanding of HDL languages (Verilog, VerilogA, and VerilogAMS). Skill, C, and SystemVerilog are a plus.
Experience with layout parasitic/leakage design trade-offs.
Solid understanding of modeling challenges for sub-micron technologies.
Understanding of device physics at the transistor design level (cross section, STI, DTI) is preferred.

Why Allegro?

Join Allegro and become part of a team where your contributions truly matter.

We foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.
Your work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.
You’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.
Join us—and help build what’s next.

Asks for

Values