Asks for

The ad says“Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.”
The ad says“Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.”
The ad says“Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.”
The ad says“Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.”
The ad says“Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.”
The ad says“Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.”
The ad says“Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).”
The ad says“Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.”
The ad says“Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.”
The ad says“Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.”
The ad says“Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.”
The ad says“Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.”
The ad says“Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.”
The ad says“Proficiency in hardware description languages such as Verilog, System Verilog.”
The ad says“Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.”
The ad says“Proficiency in hardware description languages such as Verilog, System Verilog.”

Job Details:

Job Description:

The Role and Impact:

As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified Intel Chassis designs. This position is at the forefront of Intel's innovation, ensuring that our products consistently deliver world-class performance, power efficiency, and reliability. Work closely with architects to define and design complex protocol bridges. Define and implement range-based access control for secured memory and register paths across HBW and LBW. Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths. Design and validate parity/ECC generation and checking for request, response, and data channels. Define fault behavior for unauthorized accesses and corrupt transactions, including silent block semantics, RAZWI-style handling, poison propagation, and timeout cleanup. Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling. Support error injection, diagnostics, and post-silicon debug hooks for both security and reliability validation. Define and implement telemetry capture for fabric load, latency, congestion, error context, and other operational health indicators. Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure. Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical. Integrate trigger, monitor, and logging hooks needed for bring-up, stress triage, and post-silicon correlation. Work with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are useful, stable, and diagnosable. Balance observability depth against area, timing, bandwidth, and survivability constraints. Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features.

Key Responsibilities:

Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.
Define architecture and microarchitecture features for the IP block being designed.
Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.
Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.
Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.
Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.
Support SoC customers with seamless integration and verification of IP blocks.
Telemetry and debug are both observability functions rather than primary Datapath functions.
Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.

Qualifications:

Minimum Qualifications:

Bachelor's degree in electrical engineering, Computer Engineering, or related field.
A minimum of 8 years of experience in logic design and RTL development.
Proficiency in hardware description languages such as Verilog, System Verilog.
Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
Knowledge of IP block integration workflows within SoC designs.
Expertise in RAS/debug/security/telemetry.

Preferred Qualifications:

Master's or PhD degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of professional experience encompassing complex IP logic design for high-performance applications.
Demonstrated expertise in architecture and microarchitecture definition.
Familiarity with advanced verification methodologies such as UVM or formal verification techniques.
Strong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.
A mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.

Take the next step in your career and become part of Intel's world-class engineering team, shaping the future of technology with groundbreaking innovations. Apply today to make an impact.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.