Asks for

The ad says“Strong experience in constrained-random, assertion-based, and coverage-driven verification.”
The ad says“Strong knowledge of AXI4 protocol and SoC interconnects.”
The ad says“Strong experience in constrained-random, assertion-based, and coverage-driven verification.”
The ad says“Strong experience in constrained-random, assertion-based, and coverage-driven verification.”
The ad says“Experience with gate-level simulations and timing-aware verification.”
The ad says“We are seeking an experienced Senior PCIe Verification Engineer to join our SoC Verification team. The ideal candidate should have strong expertise in PCI Express (PCIe) IP/Subsystem verification using SystemVerilog/UVM and hands-on experience in 2–3 successful SoC tape-outs. The candidate will be responsible for developing robust verification environments, driving verification closure, and ensuring first-pass silicon success for PCIe-based subsystems.”
The ad says“Solid understanding of PCIe architecture and protocol layers:”
The ad says“Hands-on experience with PCIe Verification IP (VIP).”
The ad says“Excellent RTL and protocol debugging skills.”
The ad says“Excellent RTL and protocol debugging skills.”
The ad says“We are seeking an experienced Senior PCIe Verification Engineer to join our SoC Verification team. The ideal candidate should have strong expertise in PCI Express (PCIe) IP/Subsystem verification using SystemVerilog/UVM and hands-on experience in 2–3 successful SoC tape-outs. The candidate will be responsible for developing robust verification environments, driving verification closure, and ensuring first-pass silicon success for PCIe-based subsystems.”
The ad says“We are seeking an experienced Senior PCIe Verification Engineer to join our SoC Verification team. The ideal candidate should have strong expertise in PCI Express (PCIe) IP/Subsystem verification using SystemVerilog/UVM and hands-on experience in 2–3 successful SoC tape-outs. The candidate will be responsible for developing robust verification environments, driving verification closure, and ensuring first-pass silicon success for PCIe-based subsystems.”
The ad says“Experience writing SystemVerilog Assertions (SVA).”
The ad says“Experience with gate-level simulations and timing-aware verification.”
The ad says“We are seeking an experienced Senior PCIe Verification Engineer to join our SoC Verification team. The ideal candidate should have strong expertise in PCI Express (PCIe) IP/Subsystem verification using SystemVerilog/UVM and hands-on experience in 2–3 successful SoC tape-outs. The candidate will be responsible for developing robust verification environments, driving verification closure, and ensuring first-pass silicon success for PCIe-based subsystems.”

Introduction

We are seeking an experienced Senior PCIe Verification Engineer to join our SoC Verification team. The ideal candidate should have strong expertise in PCI Express (PCIe) IP/Subsystem verification using SystemVerilog/UVM and hands-on experience in 2–3 successful SoC tape-outs. The candidate will be responsible for developing robust verification environments, driving verification closure, and ensuring first-pass silicon success for PCIe-based subsystems.

About Edgecortix

At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.

The Team

As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.

Your Role and Responsibilities:

Develop and execute comprehensive verification plans for PCIe IPs, subsystems, and SoC integration.
Build reusable SystemVerilog/UVM verification environments from scratch.
Develop constrained-random and directed test scenarios for PCIe verification.
Verify PCIe functionality across LTSSM, Link Training, Configuration Space, Enumeration, Data Link Layer, Transaction　Layer, and PHY interactions.
Verify advanced PCIe features such as MSI/MSI-X, AER, ASPM, LTR, SR-IOV, ATS, PASID, FLR, and Power Management (as applicable).
Perform protocol compliance verification using industry-standard PCIe VIPs .
Develop functional coverage models, assertions, scoreboards, monitors, and protocol checkers.
Analyze code coverage and functional coverage and drive verification closure.
Perform RTL, protocol, and UVM testbench debugging.
Support gate-level simulations, regression execution, and post-silicon bring-up activities when required.
Collaborate closely with RTL, architecture, firmware, physical design, DFT, and validation teams throughout the SoC development cycle.

Desired Qualifications:

6–12 years of experience in functional verification using SystemVerilog and UVM.
Strong expertise in PCI Express (PCIe Gen4/Gen5/Gen6) verification.
Hands-on experience with PCIe Verification IP (VIP).
Solid understanding of PCIe architecture and protocol layers:
• Physical Layer
• Data Link Layer
• Transaction Layer
• Configuration Space
• LTSSM
• Error Handling and Recovery
Experience verifying DMA-based PCIe designs and AXI-to-PCIe bridge architectures.
Strong knowledge of AXI4 protocol and SoC interconnects.
Experience writing SystemVerilog Assertions (SVA).
Strong experience in constrained-random, assertion-based, and coverage-driven verification.
Experience with gate-level simulations and timing-aware verification.
Excellent RTL and protocol debugging skills.
SoC Experience
• Hands-on experience with 2–3 successful SoC tape-outs.
• Experience verifying PCIe integration at the SoC level.
• Exposure to SoC boot flows, reset sequences, clocking architecture, interrupt handling, and subsystem integration.
• Experience working with firmware and software teams during integration and bring-up.

What’s in it for you?

Make a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.

Benefits and Perks

Highly competitive salary and stock options
Flex work time
Top-tier employee benefits