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Job Description:
Role Overview
Responsible for executing high-quality layouts across Standard Cells, I/O pads, and Mixed-Signal IP in advanced processes within project schedules.
Key Responsibilities
Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
Planning & Floorplanning: Manage schedule and execute layouts from the transistor level up including cell- and block-level floorplanning.
Collaboration: Adopt new methodologies, communicate actively across sites, and work closely with senior layout engineers.
Skill Set & Requirements
Education & Experience:
Technical Skills:
Solid grasp of Standard Cell, Memory, or Analog/Mixed-Signal layout basics.
Familiarity with basic ESD/Latch-up layout techniques and transistor-level placement.
Practical experience with physical verification: DRC, LVS, ERC, and Antenna checks.
Basic understanding or exposure to sub-micron or advanced process nodes (e.g. 5nm, 3nm, 2nm, 1.4nm ).
Tools & Concepts:
Proficient with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis.)
Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming in a plus.
Personal Attributes: Quick learner, proactive, team player, with good communication and strong problem-solving skills.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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