With our groundbreaking satellite 5G constellation, OQ Technology is a global leader in IoT communication connectivity and associated services. We are a venture capital-backed company with a successful track record of satellite launches and are the first company in the world to disrupt the telecommunications industry by merging cellular 5G with satellites.
Our technology has massive implications for the Oil & Gas, Maritime, Industry 4.0, and Transport sectors, particularly in the management and tracking of assets in remote and rural areas and in extending 5G coverage through non-terrestrial networks.
As our wireless technologies continue to evolve and earn multiple awards, with funding for the next phase secured and strong commercial traction demonstrated, we are now looking to onboard a talented FPGA Engineer to join our engineering team in Luxembourg and contribute to the continued growth and success of our organization.
The role sits within the payload and radio development group and carries hands-on responsibility for the design, implementation, integration, and verification of FPGA firmware for satellite and telecommunications applications. The engineer will work within a multidisciplinary team spanning hardware, software, RF, and systems engineering, contributing across the development lifecycle from RTL implementation and simulation through hardware bring-up and laboratory validation.
Experience in space or telecommunications applications is preferred. Candidates with a strong FPGA implementation background from adjacent domains - defence, radar, wireless infrastructure, or high-speed digital systems will be considered where the core FPGA skills are well evidenced.
The engineer will be responsible for FPGA firmware design and verification across digital signal processing, baseband, and high-speed interface functions for satellite payload and telecommunications applications. Typical tasks include:
- Architect, design, and implement FPGA firmware in VHDL and/or Verilog/SystemVerilog for digital signal processing, high-speed interfaces, and control logic.
- Optimise FPGA resource utilisation, timing closure, and power efficiency on Xilinx/AMD Zynq, Zynq UltraScale+, Kintex, Virtex, and Artix device families using Vivado and Vitis toolchains.
- Implement DSP algorithms in FPGA fabric, including filtering, modulation and demodulation, FFT, decimation, and baseband processing functions, using RTL or HLS as appropriate.
- Implement high-speed communication interfaces including AXI4, AXI-Stream, AXI-Lite, JESD204B, PCIe, Ethernet, SPI, I²C, UART, and DDR4.
- Develop testbenches and simulation environments to verify RTL behaviour against functional specifications prior to hardware integration.
- Execute functional and regression simulation using industry-standard tools, documenting results against defined acceptance criteria.
- Work with embedded processors including ARM Cortex-A53, ARM Cortex-R5, and MicroBlaze, integrating FPGA logic with Linux, RTOS, or bare-metal software environments.
- Perform FPGA bring-up, hardware debugging, and validation using Vivado Logic Analyser, Integrated Logic Analyser, oscilloscopes, and spectrum analysers.
- Implement telecommunication algorithms from MATLAB or C/C++ reference models and verify bit-accurate correspondence between reference and hardware outputs.
- Interface with RF front-end hardware to resolve firmware-hardware integration issues and ensure consistency of signal interfaces.
- Prototype solutions using SDR platforms such as Xilinx RFSoC, USRP, or Analog Devices evaluation hardware to support proof-of-concept demonstrations.
- Contribute to the maintenance and improvement of the internal test laboratory capability.
- Produce and maintain firmware implementation documentation, test plans, test reports, and configuration records.
- Contribute to design reviews, test readiness reviews, and technical progress reviews.
- Work within a multidisciplinary team spanning software, firmware, hardware, and RF engineering disciplines.
- Report regularly on implementation and test progress to the responsible senior engineer or project manager.
Mandatory:
- Bachelor’s degree in Electronic Engineering, Electrical Engineering, Computer Engineering, Telecommunications Engineering, or a closely related discipline.
- Minimum three years of demonstrable hands-on experience in FPGA firmware development, including RTL design, simulation, synthesis, and hardware bring-up.
- Proficiency in VHDL and/or Verilog/SystemVerilog for RTL design and functional simulation.
- Demonstrated experience with Xilinx/AMD FPGA device families and Vivado or Vitis toolchains, including constraint-driven implementation and timing closure.
- Working knowledge of FPGA architecture including DSP slices, block RAM, clock management resources, and high-speed serial transceivers.
- Experience developing testbenches and executing structured simulation and verification campaigns.
- Experience performing hardware bring-up and laboratory testing of FPGA-based systems.
- Familiarity with embedded processor integration within FPGA environments, including AXI-based hardware-software interfaces.
- Ability to implement and verify algorithms from MATLAB or C/C++ reference models.
- Proficiency in spoken and written English.
- Resident in Europe with valid right to work.
Desirable:
- Experience in satellite telecommunications applications, including familiarity with CCSDS, DVB-S2/S2X, DVB-RCS2, or NTN waveform standards.
- Experience with SDR platform development, including integration of baseband firmware with RF front-end hardware on platforms such as Xilinx RFSoC, USRP, or Analog Devices ADRV900x/AD936x-based systems.
- Experience with Intel/Altera FPGA device families and Quartus Prime toolchain.
- Experience with High-Level Synthesis tools including Vivado HLS or Vitis HLS.
- Experience with embedded Linux integration on Zynq or Zynq UltraScale+ platforms, including Yocto build environment and kernel driver development.
- Familiarity with ASIC-oriented RTL design practices, including synthesis to standard cell libraries, static timing analysis, DFT insertion, or power analysis using tools such as Synopsys Design Compiler or Cadence Genus.
- Exposure to radiation-tolerant or space-grade FPGA design constraints and associated verification requirements.
- Experience with wireless or telecommunications PHY layer implementation, including digital signal processing for modulation, demodulation, synchronisation, or channel estimation.
- Experience contributing to technical documentation, design reviews, or technical proposals in an engineering programme context.
- Scripting experience in Python, TCL, or Bash for build automation, test scripting, or tool integration.
Software, Hardware & Platform Skills:
- VHDL, Verilog/SystemVerilog, MATLAB, C/C++, Python.
- Xilinx/AMD Vivado, Vitis, ISE; Intel/Altera Quartus Prime.
- Xilinx/AMD device families: Zynq, Zynq UltraScale+, Kintex, Virtex, Artix, RFSoC, Versal.
- SDR platforms: Xilinx RFSoC, NI USRP, Analog Devices ADALM-PLUTO, ADRV9002/ADRV9009 evaluation platforms, GNU Radio.
- High-speed interfaces: AXI4, AXI-Stream, JESD204B, PCIe, Ethernet, DDR4, SPI, I²C, UART, SpaceWire.
- Simulation and verification: ModelSim, QuestaSim, UVVM, or equivalent HDL simulation tools.
- Laboratory test equipment: oscilloscope, spectrum analyser, network analyser, logic analyser, ILA.
- Version control: Git or equivalent.
- Operating environment: Linux.
Additional Information:
As part of the recruitment process, candidates may be required to provide a criminal record certificate issued within the last three (3) months.
- Enjoy a 50% income tax exemption on your salary - an exceptional incentive for top talent relocating to Luxembourg, subject to eligibility conditions.
- Flexibility to work remotely one day per week.
- Opportunity to work on flagship EU space mission projects.
- A dynamic, high-growth environment with career development opportunities.
- Regular company events and team activities.
