Asks for

The ad says“Must have 3+ years of experience in layout designs in advanced CMOS process.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.”
The ad says“Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.”
The ad says“Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.”
The ad says“Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.”
The ad says“Should have adequate knowledge of schematics, collaborate with circuit designer and CAD team.”
The ad says“Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.”
The ad says“Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.”
The ad says“Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.”
The ad says“Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.”
The ad says“Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.”

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned Dram product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.

Responsibilities:

Responsible for Design and development of IP layouts used in DRAM chips.
Perform layout verification like LVS/DRC/EM, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.
Guide and lead developing team members in their execution of Sub block-level layouts & review their work.
Contribute to effective project-management.
Plan and detail your layout, presenting material for global teams to review
Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.

Minimum Qualifications:

BE/BTech or MTech in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.
Must have 3+ years of experience in layout designs in advanced CMOS process.
Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.
Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
Should have adequate knowledge of schematics, collaborate with circuit designer and CAD team.
Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.
Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
Should have leadership qualities and able to do multi-tasking as required.
Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.

Preferred Qualifications:

Knowledge of Skill coding and layout automation is a plus.
Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
AI usage (Leveraging AI, Generative AI, AI-Enabled)

"The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position."

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_na@micron.com

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Asks for

Values