Asks for

The ad says“Hands-on experience with Advantest V93000 ATE platform and developing wafer sort/final test programs.”
The ad says“Digital and analog circuit-level understanding.”
The ad says“Strong academic/technical background in Electrical or Computer Engineering; Bachelor's required; MS preferred.”
The ad says“Digital and analog circuit-level understanding.”
The ad says“Strong academic/technical background in Electrical or Computer Engineering; Bachelor's required; MS preferred.”
The ad says“Strong knowledge of PCIe Gen4+, PAM4 SerDes, Ethernet (25G+), and/or LPDDR4/LPDDR5 interfaces.”
The ad says“Minimum of 12+ years of experience in post-silicon product development dealing with high-speed XCVR (product, test, or validation).”
The ad says“Strong data analysis skills using JMP, Spotfire, or equivalent tools.”
The ad says“Strong knowledge of PCIe Gen4+, PAM4 SerDes, Ethernet (25G+), and/or LPDDR4/LPDDR5 interfaces.”
The ad says“Strong knowledge of PCIe Gen4+, PAM4 SerDes, Ethernet (25G+), and/or LPDDR4/LPDDR5 interfaces.”
The ad says“Experience working with PCIe Gen4 and above.”
The ad says“Strong knowledge of PCIe Gen4+, PAM4 SerDes, Ethernet (25G+), and/or LPDDR4/LPDDR5 interfaces.”
The ad says“Minimum of 12+ years of experience in post-silicon product development dealing with high-speed XCVR (product, test, or validation).”
The ad says“Strong data analysis skills using JMP, Spotfire, or equivalent tools.”
The ad says“Strong problem-solving skills involving system-level analysis with test hardware, test programs, and DUT.”
The ad says“Hands-on experience with Advantest V93000 ATE platform and developing wafer sort/final test programs.”

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

As the Director of Product & Test Engineering, you will lead Astera Labs' Product and Test Engineering organization supporting new product introductions (NPI) and high-volume manufacturing across our Asia OSAT partners. You will build and develop a high-performing engineering team responsible for product qualification, ATE test development, characterization, yield improvement, and manufacturing support throughout the product lifecycle. Working closely with Design Engineering, Silicon Validation, Quality, Manufacturing, and Supply Chain teams, you will drive operational excellence while ensuring successful product execution and customer delivery.

Basic Qualifications

Minimum of 12+ years of experience in post-silicon product development dealing with high-speed XCVR (product, test, or validation).
Experience working with PCIe Gen4 and above.
5+ years of leadership experience managing Product and Test Engineering organizations.
Experience defining and running standards-based qualification (product and package).
Strong academic/technical background in Electrical or Computer Engineering; Bachelor's required; MS preferred.
Strong problem-solving skills involving system-level analysis with test hardware, test programs, and DUT.
Digital and analog circuit-level understanding.
Excellent communication, leadership, and cross-functional collaboration skills.

Required Experience

Build, lead, and grow a strong Product & Test Engineering organization in Taiwan.
Define engineering priorities and resource planning supporting NPI and HVM.
Proven track record supporting seamless production of semiconductor products through global OSAT partners across the complete product lifecycle.
Hands-on experience with Advantest V93000 ATE platform and developing wafer sort/final test programs.
Strong knowledge of PCIe Gen4+, PAM4 SerDes, Ethernet (25G+), and/or LPDDR4/LPDDR5 interfaces.
Drive product qualification, yield improvement, manufacturing readiness, and production release.
Partner closely with Design, Validation, Quality, Manufacturing, and Supply Chain teams to resolve product and manufacturing issues.
Strong data analysis skills using JMP, Spotfire, or equivalent tools.
Mentor engineering managers and senior engineers while building a high-performing organization.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.