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Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead) at The Boeing Company · Katori

Asks for

The ad says“Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.”
The ad says“Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Proficiency in scripting (Tcl/Perl/Python) and DFT verification methodologies.”
The ad says“Proficiency in scripting (Tcl/Perl/Python) and DFT verification methodologies.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.”
The ad says“Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.”
The ad says“Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.”
The ad says“Proficiency in scripting (Tcl/Perl/Python) and DFT verification methodologies.”
The ad says“Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.”

Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)

Company:

The Boeing Company

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple Design-for-Test (DFT) Engineers — ASIC Backend to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products to support advanced digital subsystem development in an aerospace environment in El Segundo or Huntington Beach, CA.

Position overview
The DFT team drives architecture, verification, and post-silicon validation for leading-edge ASICs. We seek engineers across experience levels (Jr → Principal) to design and validate test access mechanisms, memory BIST, scan compression, and related test infrastructure.

Key responsibilities

Design and implement DFT architectures: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression
Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation
Drive pattern generation, coverage optimization, memory test validation, and silicon debug (scan, at-speed, bring-up)
Integrate DFT features across the chip design flow and collaborate with cross-functional teams to ensure robust DFT integration
Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable
Contribute to development and deployment of DFT methodologies for next-generation products
Occasional travel and after-hours meetings during critical milestones

Boeing continuously shapes the future of aerospace and space systems, advancing U.S. leadership in space while amplifying human creativity and intelligence. As a Boeing engineer, you’ll join a diverse, collaborative team solving high‑impact challenges in complex semiconductor design. If you value a company that supports strong work–life balance and meaningful technical work, Boeing is the place to be.

How to make your application stand out:
If you are a creative, autonomous engineer passionate about advancing DFT for mission-critical ASICs, we want to hear from you. Please include a cover letter/brief summary of relevant DFT experience when submitting your application.

This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed locations.

Basic Qualifications (Required Skills/Experience):

This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
2+ years of experience in Design for Testability (DFT) or equivalent (role level adjustable by experience).
Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes.
Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug.
Proficiency in scripting (Tcl/Perl/Python) and DFT verification methodologies.
Excellent analytical, problem-solving, and communication skills.

Preferred Qualifications (Desired Skills/Experience):

Experienced, Level 3: 5+ years of related engineering experience
Lead, Level 4: 9+ years of related engineering experience
Bachelor’s Degree or Master's Degree in EE, Computer Engineering/Science, or related field
Active U.S. Secret Security Clearance
Requirements development and traceability experience
FPGA implementation including constraints and timing closure
Static timing analysis experience
Understanding of timing fundamentals and CDC concepts
Verification collaboration experience
High-speed interfaces, processor integration, memory subsystems, or SoC integration
Mentoring or technical leadership exposure
Familiarity with industry-standard tools and methodologies

Conflict of Interest:

Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.

Typical Education/Experience:

Associate, Level 2: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 2 or more years' related work experience or an equivalent combination of technical education and experience (e.g. Master). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Relocation:

This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.

Drug Free Workplace:

Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.

Shift Work:

This position is for 1st shift.

Total Rewards:

At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.

Pay is based upon candidate experience and qualifications, as well as market and business considerations.

Summary pay range for Associate, (Level 2): $98,600 - $133,400

Summary pay range for Experienced, (Level 3): $119,850 - $162,150

Summary pay range for Lead, (Level 4): $146,200 - $197,800

Language Requirements:

Not Applicable

Education:

Bachelor's Degree or Equivalent

Relocation:

This position offers relocation based on candidate eligibility.

Export Control Requirement:

This position must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements, a “U.S. Person” as defined by 22 C.F.R. §120.62 is required. “U.S. Person” includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee.

Safety Sensitive:

This is not a Safety Sensitive Position.

Security Clearance:

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.

Visa Sponsorship:

Employer will not sponsor applicants for employment visa status.

Contingent Upon Award Program

This position is not contingent upon program award

Shift:

Shift 1 (United States of America)

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Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.

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