Asks for

The ad says“Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.”
The ad says“Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.”
The ad says“Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators.”
The ad says“Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.”
The ad says“5+ years of experience in CPU design for high-performance computing and AI acceleration.”
The ad says“Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators.”
The ad says“Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.”
The ad says“Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.”
The ad says“5+ years of experience in CPU design for high-performance computing and AI acceleration.”
The ad says“Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.”
The ad says“Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.”
The ad says“Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.”
The ad says“Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators.”
The ad says“RTL design with cutting edge AI frontier models.”
The ad says“Experience with RTL development with cutting edge AI frontier models.”
The ad says“Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.”
The ad says“Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.”

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads. Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms. This role is ideal for an architect/micro-architect who enjoys working across hardware and software boundaries, defining next-generation compute architectures, and shaping how CPUs and HPC/AI workloads work together.

This role is remote, based out of North America or Spain.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems.
Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.
Comfortable making architectural decisions across CPU cluster and subsystems.
Collaborative technical leader who enjoys influencing cross-functional engineering teams.
Curious and driven to solve challenging performance, scalability, and system architecture problems.

What We Need

5+ years of experience in CPU design for high-performance computing and AI acceleration.
Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.
Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators.
Experience defining architectural specifications and leading cross-functional teams from concept through silicon implementation.
Experience with RTL development with cutting edge AI frontier models.

What You Will Learn

Design CPU compute that efficiently accelerates modern HPC/AI workloads through optimized matrix floating-point execution and heterogeneous compute architectures.
Gain deep expertise in the co-design of CPUs, AI accelerators, and memory subsystems.
Learn how large-scale HPC, and AI workloads influence hardware architecture, data movement, and system-level optimization.
Work alongside world-class CPU, AI, and system architects defining the future of open RISC-V computing and AI infrastructure.
RTL design with cutting edge AI frontier models.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.