Asks for

The ad says“Proven track record with bump planning, RDL implementation, and multi-voltage domain designs”
The ad says“Bachelors in Electrical Engineering and 12+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning”
The ad says“Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning”
The ad says“Bachelors in Electrical Engineering and 12+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning”
The ad says“Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes”
The ad says“Experience in scripting languages like Python, Tcl, or Perl and EDA tools”
The ad says“Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning”
The ad says“Proven track record with bump planning, RDL implementation, and multi-voltage domain designs”
The ad says“Bachelors in Electrical Engineering and 12+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning”
The ad says“Experience in scripting languages like Python, Tcl, or Perl and EDA tools”
The ad says“Bachelors in Electrical Engineering and 12+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning”
The ad says“Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning”
The ad says“Experience in scripting languages like Python, Tcl, or Perl and EDA tools”
The ad says“Proven track record with bump planning, RDL implementation, and multi-voltage domain designs”
The ad says“Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning”
The ad says“Experience in scripting languages like Python, Tcl, or Perl and EDA tools”
The ad says“Bachelors in Electrical Engineering and 12+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning”
The ad says“Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning”

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products. More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.

Responsibilities:

Own chip floor planning, partition creation, clock tree and delivery of top level partitions
Resolve physical design issues related to chip integration and assembly
Manage all cross functional interactions related to top level floorplanning, I/O and bump planning with package team
Develop and improve floorplan implementation methodologies using both industry and internal tools
Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specification

Preferred qualifications:

Bachelors in Electrical Engineering and 12+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
Or Master's degree in Electrical Engineering and 10+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc)
Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes
Proven track record with bump planning, RDL implementation, and multi-voltage domain designs
Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning
Experience in collaborating with design, package and methodology teams during development phase
Experience in scripting languages like Python, Tcl, or Perl and EDA tools
Must work in person at our San Jose site and no remote work option

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $143,800 - $230,000.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.