Asks for

The ad says“5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role.”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).”
The ad says“Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).”
The ad says“Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).”
The ad says“Strong scripting and automation skills—Python, TCL, Make, or shell—for building flows, regressions, and debug tooling.”
The ad says“5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role.”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Strong scripting and automation skills—Python, TCL, Make, or shell—for building flows, regressions, and debug tooling.”
The ad says“Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.”
The ad says“Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.”
The ad says“Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).”
The ad says“Strong scripting and automation skills—Python, TCL, Make, or shell—for building flows, regressions, and debug tooling.”
The ad says“5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role.”
The ad says“Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.”
The ad says“Strong scripting and automation skills—Python, TCL, Make, or shell—for building flows, regressions, and debug tooling.”
The ad says“Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.”
The ad says“Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).”
The ad says“Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.”
The ad says“Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.”
The ad says“Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.”

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

About the Role

We’re looking for an Applications Engineer who will help customers successfully evaluate, integrate, verify, and physically implement our silicon IP in their SoCs. You’ll be the technical bridge between customers and our design, verification, physical design, and characterization teams—helping customers stand up verification environments, close coverage and timing, resolve integration issues, and keep tapeouts on schedule. This customer-facing role combines broad ASIC/SoC expertise, hands-on problem solving, and clear technical communication.

What You’ll Do

Serve as the primary technical point of contact for customers integrating our silicon IP, from RTL simulation and UVM testbench setup through synthesis, floorplanning, place-and-route, timing closure, and signoff.
Debug customer-reported issues across the RTL, testbench, constraints, and physical implementation boundary; distinguish IP defects and deliverable issues from configuration errors, protocol misunderstandings, constraints, or implementation choices.
Develop and maintain reference verification environments, example testbenches, implementation flows, floorplan guidance, and integration collateral—including SDC and UPF templates—that reduce customer ramp time.
Deliver onsite and remote technical training on IP architecture, verification methodology, verification IP usage, coverage closure, timing models, physical abstracts, and implementation best practices.
Partner with engineering and product leaders to aggregate field evidence, prioritize corrective work, and shape future capabilities, deliverables, and release content.
Support pre-sales technical evaluations by helping prospective customers assess IP quality, verification collateral, PPA, floorplan compatibility, node/process readiness, and integration effort.
Lead architecture-to-signoff reviews of customer integrations, identify implementation risks, and recommend corrective actions across configuration, verification, performance, timing, power, and area.
Exercise upcoming IP releases and customer collateral in representative integration flows; document gaps and work with engineering owners to close them before external delivery.
Advise customers on interface and protocol integration, multi-voltage and power-domain design, DFT stitching at the IP boundary, and node-specific signoff requirements.
Turn recurring support cases into reusable enablement—including reference examples, diagnostic playbooks, automation, and self-service guidance—that shortens resolution time for customers and the field team.
Track and report field issues and recurring integration patterns to inform the IP roadmap, deliverable quality, and process-node support priorities.

What You’ll Bring

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role.
Strong scripting and automation skills—Python, TCL, Make, or shell—for building flows, regressions, and debug tooling.
Hands-on experience integrating third-party or internally licensed silicon IP, such as soft or hard macros, protocol or interface IP, interconnect, standard-cell libraries, or memory compilers.
Experience diagnosing complex integration issues and translating deep technical findings into clear, actionable guidance for customers and internal teams.
Familiarity with multiple foundries or process nodes and the verification, PPA, reliability, and signoff challenges associated with them.
One or more of the following experience areas:

Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.
Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.
Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).

Willingness to travel to customer sites approximately 20–30%, depending on business needs.

Nice to Have

Experience as an IP vendor applications engineer, verification or physical-design consultant, or silicon IP integrator at a systems/SoC company.
Experience with formal verification, protocol compliance suites, verification IP, low-power design, SoC-level DFT, or reliability signoff.
Experience with processor-based SoC integration, cache-coherent fabrics, and high-speed chip-to-chip or peripheral interfaces relevant to Efficient’s platform.
Public speaking, technical training, or conference presentation experience

We offer a competitive base salary for this role, generally ranging from $160,000 to $230,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.

Why Join Efficient?

Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.