Application Engineer - digital implementation

Asks for

• CTSThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• floorplan and partitionThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• mixed signal designThe ad says“4. Assist in technical evaluation, assessment and delivery of concurrent mixed signal design.”
• PerlThe ad says“• Be familiar with shell/Perl/Tcl/Python etc. script language.”
• Physical verificationThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• placeThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• Power Network analysisThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• programming languagesThe ad says“• Requires working knowledge of one or more programming languages, and effective communication and soft skills.”
• PythonThe ad says“• Be familiar with shell/Perl/Tcl/Python etc. script language.”
• RC extractionThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• routeThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• RTL-to-GDSII design methodologyThe ad says“2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs.”
• shellThe ad says“• Be familiar with shell/Perl/Tcl/Python etc. script language.”
• STA timing closureThe ad says“3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus.”
• TclThe ad says“• Be familiar with shell/Perl/Tcl/Python etc. script language.”