Asks for

The ad says“You hold an M.Sc. in Electronics Engineering, Microelectronics or a related field, or have gained equivalent expertise through relevant industry experience. You have at least three years of professional experience in analog IC design, including transistor-level design, schematic development and simulation.”
The ad says“You have a good understanding of CMOS circuit design and are comfortable analyzing simulation results and optimizing circuits for power, performance and area. You have experience with Cadence Virtuoso, Spectre or comparable EDA tools, along with an understanding of how physical layout and parasitic effects influence circuit performance.”
The ad says“You have a good understanding of CMOS circuit design and are comfortable analyzing simulation results and optimizing circuits for power, performance and area. You have experience with Cadence Virtuoso, Spectre or comparable EDA tools, along with an understanding of how physical layout and parasitic effects influence circuit performance.”
The ad says“You have a good understanding of CMOS circuit design and are comfortable analyzing simulation results and optimizing circuits for power, performance and area. You have experience with Cadence Virtuoso, Spectre or comparable EDA tools, along with an understanding of how physical layout and parasitic effects influence circuit performance.”
The ad says“You hold an M.Sc. in Electronics Engineering, Microelectronics or a related field, or have gained equivalent expertise through relevant industry experience. You have at least three years of professional experience in analog IC design, including transistor-level design, schematic development and simulation.”
The ad says“You hold an M.Sc. in Electronics Engineering, Microelectronics or a related field, or have gained equivalent expertise through relevant industry experience. You have at least three years of professional experience in analog IC design, including transistor-level design, schematic development and simulation.”
The ad says“You have a good understanding of CMOS circuit design and are comfortable analyzing simulation results and optimizing circuits for power, performance and area. You have experience with Cadence Virtuoso, Spectre or comparable EDA tools, along with an understanding of how physical layout and parasitic effects influence circuit performance.”
The ad says“You hold an M.Sc. in Electronics Engineering, Microelectronics or a related field, or have gained equivalent expertise through relevant industry experience. You have at least three years of professional experience in analog IC design, including transistor-level design, schematic development and simulation.”

Values

The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”
The ad says“Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.”

How do you design memory technology that delivers high performance while keeping power consumption and silicon area to a minimum? At Xenergic, it starts with a deep understanding of analog circuits, advanced semiconductor technology and the ability to turn complex design challenges into working solutions. We are now looking for an Analog Design Engineer to join our team in Lund and contribute to the development of our next generation of on-chip memory IP.

YOU WILL

Xenergic is a Lund-based semiconductor company developing high-speed, low-power on-chip memory IP for advanced chip technologies. Our engineering teams work with technology that ranges from transistor-level circuit design to physical implementation, verification and integration into customers' products.

As an Analog Design Engineer, you will join a specialised engineering team developing and optimising the analog circuits behind Xenergic's memory technology. You will contribute to new designs and improvements to existing solutions, using your understanding of the broader memory architecture to guide design decisions.

Your main responsibilities will be to:

Design and optimise analog circuits and custom IC blocks for advanced SRAM and memory IP.
Work with transistor-level and schematic design, including circuit simulation and verification across different operating conditions.
Analyse circuit behaviour and optimise designs for power consumption, performance, silicon area and reliability.
Contribute to physical layout, design verification and analysis of layout-related effects, including parasitics and EMIR.
Support the development and adaptation of memory IP across different semiconductor process technologies.
Collaborate with colleagues across analog, digital, layout and verification to solve technical challenges and support integration into customer designs.

You will join an analog team of six engineers with different technical backgrounds and experience. The team holds regular technical discussions to share challenges, design decisions and possible improvements. Much of the work requires independent problem-solving, alongside close collaboration to develop the technology. Depending on the project, you may also participate in technical discussions with customers.

The position is full-time and based on-site at Xenergic's office in Lund.

YOU ARE

You hold an M.Sc. in Electronics Engineering, Microelectronics or a related field, or have gained equivalent expertise through relevant industry experience. You have at least three years of professional experience in analog IC design, including transistor-level design, schematic development and simulation.

You have a good understanding of CMOS circuit design and are comfortable analyzing simulation results and optimizing circuits for power, performance and area. You have experience with Cadence Virtuoso, Spectre or comparable EDA tools, along with an understanding of how physical layout and parasitic effects influence circuit performance.

Experience in SRAM or memory design is an advantage but not required. Knowledge of advanced technology nodes, FinFET, DRC/LVS, EMIR-aware design, silicon measurements or scripting languages such as Python, Shell or SKILL would also be an advantage.

As a person, you are curious, analytical and enjoy understanding how things work, from individual circuits to broader architecture. You take ownership of your work, enjoy solving problems independently and value collaboration with colleagues. You are comfortable working in a smaller organization where learning, flexibility and sharing knowledge are part of everyday work. Fluency in English is required.

At Xenergic, you will work alongside experienced engineers in a highly specialized environment where your ideas and technical contributions can make a real difference. You will have the opportunity to influence the development of advanced memory technology and see your work become part of products used by customers around the world.

WANT TO KNOW MORE?

In this recruitment, Xenergic is collaborating with Nexer Recruit. Applications are reviewed continuously, so please submit your application as soon as possible. For questions about the role or the recruitment process, please contact recruitment consultant Johanna Värmfors at johanna.varmfors@nexergroup.com or +46 730 821 230, or Artan Bitiqi at artan.bitiqi@nexergroup.com or +46 723 61 28 44.

We look forward to hearing from you.

ABOUT XENERGIC

Xenergic is a Swedish deep-tech semiconductor technology company based in Lund, developing high-speed and low-power on-chip memory IP for advanced semiconductor applications. Its technology addresses important challenges in modern chip design, where performance, power consumption and silicon area are becoming increasingly important. Xenergic's solutions are relevant for applications ranging from IoT and mobile devices to networking, high-performance computing and AI.