Asks for

The ad says“Understanding of the full ASIC design flow, from specification to tape-out.”
The ad says“Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.”
The ad says“Familiarity with standard EDA tools for simulation, synthesis, linting, and clock domain crossing (CDC) analysis.”
The ad says“Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.”
The ad says“Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.”
The ad says“Lead the detailed micro-architecture definition and top-level integration of digital blocks, including CPU, memory subsystems, and interfaces.”
The ad says“Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.”
The ad says“Drive and perform hands-on RTL design for complex, timing-critical SoC blocks and digital interfaces, ensuring power, performance, and area (PPA) targets are met.”
The ad says“Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.”
The ad says“As a Member of Technical Staff, Digital Design Engineer, you will be a foundational member of our small, multi-disciplinary R&D team. We are looking for accomplished and highly motivated individuals with a strong understanding of SoC design who are excited to tackle the hardest, most ambiguous technical challenges at the intersection of AI, physics, and computer architecture. You will be responsible for driving invention, prototyping, and validation of the core components of our novel computing platform.”
The ad says“Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.”
The ad says“Create block-level timing constraints”
The ad says“Expertise in Verilog RTL coding and digital design fundamentals.”

About Unconventional

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation - a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.

The Role

As a Member of Technical Staff, Digital Design Engineer, you will be a foundational member of our small, multi-disciplinary R&D team. We are looking for accomplished and highly motivated individuals with a strong understanding of SoC design who are excited to tackle the hardest, most ambiguous technical challenges at the intersection of AI, physics, and computer architecture. You will be responsible for driving invention, prototyping, and validation of the core components of our novel computing platform.

Responsibilities

Digital Design:
- Lead the detailed micro-architecture definition and top-level integration of digital blocks, including CPU, memory subsystems, and interfaces.
- Own for the integration of third-party IP into the main SoC fabric.

Technical Leadership & Mentoring:
- Provide technical guidance and mentorship to junior digital design engineers.
- Contribute to setting best practices for design methodologies, code reviews, and quality assurance processes.
- Enhance and contribute to early stage design infrastructure for rapid tapeout.

Hands-on RTL Implementation:
- Drive and perform hands-on RTL design for complex, timing-critical SoC blocks and digital interfaces, ensuring power, performance, and area (PPA) targets are met.
- Implement and debug key digital interfaces

Synthesis & Timing:

Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.
Create block-level timing constraints
Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.

Design Verification (DV) Support:

Participate in the block-level verification plan and help develop a robust verification environment.
Triage and debug complex simulation failures to ensure functional correctness.

Physical Design Interface:
- Facilitate seamless hand-off between internal design and internal or external physical implementation teams (synthesis, timing closure).

Minimum Qualifications

Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
Experience: 8+ years of industry experience in digital ASIC/SoC design.
Strong Technical Expertise:

Expertise in Verilog RTL coding and digital design fundamentals.

Design Flow Proficiency:

Familiarity with standard EDA tools for simulation, synthesis, linting, and clock domain crossing (CDC) analysis.
Understanding of the full ASIC design flow, from specification to tape-out.

Communication: Excellent written and verbal communication skills.
Leadership: ability to lead junior engineers to achieve team goals, and to assist in the development of their skills.

Preferred Qualifications (Nice to Have)

Experience with creating digital designs, including synchronous and asynchronous logic, state machines, and bus protocols.
Experience developing scripts or tooling for design automation.
Experience optimizing designs for performance, power, or area.
Experience with modern design methods, including generative AI code development platforms.
Experience with analog mixed signal technology and interfaces.

Why Join Us?

The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale.
The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change.
The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields.
The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.