Asks for

The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“Strong experience with thermal and mechanical finite-element modeling of packages, including temperature distribution, warpage, stress, strain, fatigue, and interfacial reliability.”
The ad says“Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.”
The ad says“In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.”
The ad says“Demonstrated experience leading package failure investigations, performing root-cause analysis, and implementing effective design, material, process, or manufacturing corrective actions.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”
The ad says“Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.”
The ad says“8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.”

About the Team:

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

Role Overview

We are seeking a Package Reliability Engineer to lead reliability engineering for advanced packages used in high-performance AI and computing systems. The primary focus of this role is to assess package level mechanical and thermal reliability risks and apply thermal and mechanical modeling to optimize package design, material selection, and assembly processes. The engineer will also develop reliability test plans with external partners, identify failure mechanisms, perform root-cause analysis, and recommend practical corrective actions.

In this role, you will assess package reliability risks from early architecture development through product qualification and high-volume manufacturing. You will work closely with package design, silicon design, system engineering, manufacturing, and ASIC partners to predict package behavior, develop qualification strategies, resolve reliability issues, and improve overall package robustness and lifetime.

In this role you will:

Lead reliability test plan and assessments for advanced HPC packages, including risk identification, potential failure-mechanism analysis, root-cause investigation, mitigation planning, and corrective-action development.
Drive reliability-focused package design optimization based on thermo-mechanical modeling to improve package reliability, power integrity, thermal performance, mechanical robustness, and platform scalability.
Develop, validate, and apply package reliability models and lifetime-prediction methodologies for assembly, qualification, and product operating conditions.
Evaluate and recommend package architectures, structural designs, materials, and assembly processes to maximize reliability performance and manufacturing robustness.
Predict electromigration lifetime of package interconnects under product-specific current, temperature, workload, duty-cycle, and PCB boundary conditions.

You might thrive in this role if you have:

Enjoy solving complex reliability challenges associated with cutting-edge HPC packages, including very large package form factors, high power, and high-speed chip integration.
Are excited to develop new reliability test methodologies, predictive models, and engineering solutions rather than relying solely on conventional industry practices.
Are motivated by pushing the limits of heterogeneous verfical integration (chip/package/system), high-current power delivery, advanced cooling, and large-scale package architectures.
Want to influence product architecture and design decisions through simulation-driven insights across chip, package, cooling, and system levels.
Enjoy learning broadly across semiconductor technologies, including chip architecture, power delivery, package integration, materials, cooling, and system-level interactions.

Minimum Qualifications

8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.
In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.
Demonstrated experience leading package failure investigations, performing root-cause analysis, and implementing effective design, material, process, or manufacturing corrective actions.
Strong experience with thermal and mechanical finite-element modeling of packages, including temperature distribution, warpage, stress, strain, fatigue, and interfacial reliability.
Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.

Preferred Qualifications

Experience developing electromigration or interconnect lifetime models for solder joints, vias, redistribution layers, interposers, or package power-delivery structures.
Knowledge of package qualification methods, acceleration models, thermal cycling, power cycling, current-stress testing, and reliability lifetime extrapolation.
Familiarity with package failure-analysis techniques such as acoustic microscopy, X-ray imaging, cross-sectioning, scanning electron microscopy, and material characterization.
Experience supporting package-integrated voltage regulation, high-current power delivery, or high-transient-current AI and HPC products.
MS or PhD in Mechanical Engineering, Electrical Engineering, Materials Science, Physics, or a related technical field.
Strong communication, cross-functional collaboration, and technical leadership skills.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement.

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

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We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link.

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At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.